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[PATCH v11 02/16] target/riscv: fix clzw implementation to operate on ar
From: |
Philipp Tomsich |
Subject: |
[PATCH v11 02/16] target/riscv: fix clzw implementation to operate on arg1 |
Date: |
Sat, 11 Sep 2021 16:00:02 +0200 |
The refactored gen_clzw() uses ret as its argument, instead of arg1.
Fix it.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
(no changes since v10)
Changes in v10:
- New patch, fixing regressions discovered with x264_r.
target/riscv/insn_trans/trans_rvb.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index c0a6e25826..6c85c89f6d 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -349,7 +349,7 @@ GEN_TRANS_SHADD(3)
static void gen_clzw(TCGv ret, TCGv arg1)
{
- tcg_gen_clzi_tl(ret, ret, 64);
+ tcg_gen_clzi_tl(ret, arg1, 64);
tcg_gen_subi_tl(ret, ret, 32);
}
--
2.25.1
- [PATCH v11 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/09/11
- [PATCH v11 02/16] target/riscv: fix clzw implementation to operate on arg1,
Philipp Tomsich <=
- [PATCH v11 01/16] target/riscv: Introduce temporary in gen_add_uw(), Philipp Tomsich, 2021/09/11
- [PATCH v11 13/16] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/09/11
- [PATCH v11 06/16] target/riscv: Remove the W-form instructions from Zbs, Philipp Tomsich, 2021/09/11
- [PATCH v11 05/16] target/riscv: Reassign instructions to the Zba-extension, Philipp Tomsich, 2021/09/11
- [PATCH v11 10/16] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/09/11
- [PATCH v11 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]), Philipp Tomsich, 2021/09/11
- [PATCH v11 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/09/11
- [PATCH v11 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Philipp Tomsich, 2021/09/11
- [PATCH v11 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/11