[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v11 01/16] target/riscv: Introduce temporary in gen_add_uw()
|
From: |
Philipp Tomsich |
|
Subject: |
[PATCH v11 01/16] target/riscv: Introduce temporary in gen_add_uw() |
|
Date: |
Sat, 11 Sep 2021 16:00:01 +0200 |
Following the recent changes in translate.c, gen_add_uw() causes
failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these
regressions by introducing a temporary.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
(no changes since v10)
Changes in v10:
- new patch
target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index b72e76255c..c0a6e25826 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -624,8 +624,10 @@ GEN_TRANS_SHADD_UW(3)
static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
{
- tcg_gen_ext32u_tl(arg1, arg1);
- tcg_gen_add_tl(ret, arg1, arg2);
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext32u_tl(t, arg1);
+ tcg_gen_add_tl(ret, t, arg2);
+ tcg_temp_free(t);
}
static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
--
2.25.1
- [PATCH v11 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/09/11
- [PATCH v11 02/16] target/riscv: fix clzw implementation to operate on arg1, Philipp Tomsich, 2021/09/11
- [PATCH v11 01/16] target/riscv: Introduce temporary in gen_add_uw(),
Philipp Tomsich <=
- [PATCH v11 13/16] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/09/11
- [PATCH v11 06/16] target/riscv: Remove the W-form instructions from Zbs, Philipp Tomsich, 2021/09/11
- [PATCH v11 05/16] target/riscv: Reassign instructions to the Zba-extension, Philipp Tomsich, 2021/09/11
- [PATCH v11 10/16] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/09/11
- [PATCH v11 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]), Philipp Tomsich, 2021/09/11
- [PATCH v11 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/09/11
- [PATCH v11 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Philipp Tomsich, 2021/09/11
- [PATCH v11 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/11