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[RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR fo
From: |
Bin Meng |
Subject: |
[RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset |
Date: |
Sat, 18 Sep 2021 11:26:51 +0800 |
The reset value of IPIDR should be zero for Freescale chipset, per
the following 2 manuals I checked:
- P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
- P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)
Currently it is set to 1, which leaves the IPI enabled on core 0
after power-on reset. Such may cause unexpected interrupt to be
delivered to core 0 if the IPI is triggered from core 0 to other
cores later.
Fixes: ffd5e9fe0276 ("openpic: Reset IRQ source private members")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/584
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/intc/openpic.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c
index 9b4c17854d..2790c6710a 100644
--- a/hw/intc/openpic.c
+++ b/hw/intc/openpic.c
@@ -1276,6 +1276,15 @@ static void openpic_reset(DeviceState *d)
break;
}
+ /* Mask all IPI interrupts for Freescale OpenPIC */
+ if ((opp->model == OPENPIC_MODEL_FSL_MPIC_20) ||
+ (opp->model == OPENPIC_MODEL_FSL_MPIC_42)) {
+ if (i >= opp->irq_ipi0 && i < opp->irq_tim0) {
+ write_IRQreg_idr(opp, i, 0);
+ continue;
+ }
+ }
+
write_IRQreg_idr(opp, i, opp->idr_reset);
}
/* Initialise IRQ destinations */
--
2.25.1
- [RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset,
Bin Meng <=