Re: [RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset

[David Gibson]

On Tue, Sep 21, 2021 at 10:13:36AM +0200, Philippe Mathieu-Daudé wrote:
> On 9/21/21 05:25, David Gibson wrote:
> > On Sat, Sep 18, 2021 at 11:26:51AM +0800, Bin Meng wrote:
> > > The reset value of IPIDR should be zero for Freescale chipset, per
> > > the following 2 manuals I checked:
> > > 
> > > - P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
> > > - P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)
> > > 
> > > Currently it is set to 1, which leaves the IPI enabled on core 0
> > > after power-on reset. Such may cause unexpected interrupt to be
> > > delivered to core 0 if the IPI is triggered from core 0 to other
> > > cores later.
> > > 
> > > Fixes: ffd5e9fe0276 ("openpic: Reset IRQ source private members")
> > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/584
> > > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > 
> > Since these patches are very simple and look sensible, I've applied
> > them to ppc-for-6.2.
> > 
> > However, you should note that Greg and I are both moving into other
> > areas and don't have much capacity for ppc maintainership any more.
> > Therefore I'll shortly be sending some MAINTAINERS updates moving
> > openpic (amongst other things) to "Orphan" status.
> 
> I'm not trying to force Bin to become (yet) another maintainer,
> but from his previous contributions, he demonstrated a very good
> knowledge of embedded PowerPC ISA & chipsets, his patches have good
> quality and description, and he is consistent over time in his
> contributions. So if he is interested, I'd vouch for him as a
> maintainer for embedded ppc. Now up to him, his time and/or employer
> :)

Ok, works for me if he's interested.

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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