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[PATCH 18/30] tcg/loongarch: Implement mul/mulsh/muluh/div/divu/rem/remu
From: |
WANG Xuerui |
Subject: |
[PATCH 18/30] tcg/loongarch: Implement mul/mulsh/muluh/div/divu/rem/remu ops |
Date: |
Mon, 20 Sep 2021 16:04:39 +0800 |
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
tcg/loongarch/tcg-target-con-set.h | 1 +
tcg/loongarch/tcg-target.c.inc | 65 ++++++++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/tcg/loongarch/tcg-target-con-set.h
b/tcg/loongarch/tcg-target-con-set.h
index 58b5c487e2..57b2846d82 100644
--- a/tcg/loongarch/tcg-target-con-set.h
+++ b/tcg/loongarch/tcg-target-con-set.h
@@ -23,3 +23,4 @@ C_O1_I2(r, r, rU)
C_O1_I2(r, r, rZ)
C_O1_I2(r, 0, rZ)
C_O1_I2(r, rZ, rN)
+C_O1_I2(r, rZ, rZ)
diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc
index e5518c0102..eaa155ad68 100644
--- a/tcg/loongarch/tcg-target.c.inc
+++ b/tcg/loongarch/tcg-target.c.inc
@@ -629,6 +629,55 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_mul_i32:
+ tcg_out_opc_mul_w(s, a0, a1, a2);
+ break;
+ case INDEX_op_mul_i64:
+ tcg_out_opc_mul_d(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_mulsh_i32:
+ tcg_out_opc_mulh_w(s, a0, a1, a2);
+ break;
+ case INDEX_op_mulsh_i64:
+ tcg_out_opc_mulh_d(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_muluh_i32:
+ tcg_out_opc_mulh_wu(s, a0, a1, a2);
+ break;
+ case INDEX_op_muluh_i64:
+ tcg_out_opc_mulh_du(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_div_i32:
+ tcg_out_opc_div_w(s, a0, a1, a2);
+ break;
+ case INDEX_op_div_i64:
+ tcg_out_opc_div_d(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_divu_i32:
+ tcg_out_opc_div_wu(s, a0, a1, a2);
+ break;
+ case INDEX_op_divu_i64:
+ tcg_out_opc_div_du(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_rem_i32:
+ tcg_out_opc_mod_w(s, a0, a1, a2);
+ break;
+ case INDEX_op_rem_i64:
+ tcg_out_opc_mod_d(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_remu_i32:
+ tcg_out_opc_mod_wu(s, a0, a1, a2);
+ break;
+ case INDEX_op_remu_i64:
+ tcg_out_opc_mod_du(s, a0, a1, a2);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@@ -715,6 +764,22 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_sub_i64:
return C_O1_I2(r, rZ, rN);
+ case INDEX_op_mul_i32:
+ case INDEX_op_mul_i64:
+ case INDEX_op_mulsh_i32:
+ case INDEX_op_mulsh_i64:
+ case INDEX_op_muluh_i32:
+ case INDEX_op_muluh_i64:
+ case INDEX_op_div_i32:
+ case INDEX_op_div_i64:
+ case INDEX_op_divu_i32:
+ case INDEX_op_divu_i64:
+ case INDEX_op_rem_i32:
+ case INDEX_op_rem_i64:
+ case INDEX_op_remu_i32:
+ case INDEX_op_remu_i64:
+ return C_O1_I2(r, rZ, rZ);
+
default:
g_assert_not_reached();
}
--
2.33.0
- [PATCH 19/30] tcg/loongarch: Implement br/brcond ops, (continued)
- [PATCH 19/30] tcg/loongarch: Implement br/brcond ops, WANG Xuerui, 2021/09/20
- [PATCH 17/30] tcg/loongarch: Implement neg/add/sub ops, WANG Xuerui, 2021/09/20
- [PATCH 11/30] tcg/loongarch: Implement sign-/zero-extension ops, WANG Xuerui, 2021/09/20
- [PATCH 20/30] tcg/loongarch: Implement setcond ops, WANG Xuerui, 2021/09/20
- [PATCH 15/30] tcg/loongarch: Implement clz/ctz ops, WANG Xuerui, 2021/09/20
- [PATCH 18/30] tcg/loongarch: Implement mul/mulsh/muluh/div/divu/rem/remu ops,
WANG Xuerui <=
- [PATCH 08/30] tcg/loongarch: Implement the memory barrier op, WANG Xuerui, 2021/09/20
- [PATCH 24/30] tcg/loongarch: Implement tcg_target_qemu_prologue, WANG Xuerui, 2021/09/20
- [PATCH 28/30] configure, meson.build: Mark support for 64-bit LoongArch hosts, WANG Xuerui, 2021/09/20