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[PULL 23/27] target/arm: Optimize MVE VMVN
From: |
Peter Maydell |
Subject: |
[PULL 23/27] target/arm: Optimize MVE VMVN |
Date: |
Mon, 20 Sep 2021 15:19:43 +0100 |
Optimize the MVE VMVN insn by using TCG vector ops when possible.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-9-peter.maydell@linaro.org
---
target/arm/translate-mve.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 13de55242e2..4583e22f21c 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -769,7 +769,7 @@ static bool trans_VREV64(DisasContext *s, arg_1op *a)
static bool trans_VMVN(DisasContext *s, arg_1op *a)
{
- return do_1op(s, a, gen_helper_mve_vmvn);
+ return do_1op_vec(s, a, gen_helper_mve_vmvn, tcg_gen_gvec_not);
}
static bool trans_VABS_fp(DisasContext *s, arg_1op *a)
--
2.20.1
- [PULL 16/27] target/arm: Avoid goto_tb if we're trying to exit to the main loop, (continued)
- [PULL 16/27] target/arm: Avoid goto_tb if we're trying to exit to the main loop, Peter Maydell, 2021/09/20
- [PULL 26/27] target/arm: Optimize MVE VSLI and VSRI, Peter Maydell, 2021/09/20
- [PULL 19/27] target/arm: Optimize MVE logic ops, Peter Maydell, 2021/09/20
- [PULL 17/27] target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration, Peter Maydell, 2021/09/20
- [PULL 22/27] target/arm: Optimize MVE VDUP, Peter Maydell, 2021/09/20
- [PULL 25/27] target/arm: Optimize MVE VSHLL and VMOVL, Peter Maydell, 2021/09/20
- [PULL 02/27] elf2dmp: Fail cleanly if PDB file specifies zero block_size, Peter Maydell, 2021/09/20
- [PULL 14/27] arm: Add Hypervisor.framework build target, Peter Maydell, 2021/09/20
- [PULL 18/27] target/arm: Add TB flag for "MVE insns not predicated", Peter Maydell, 2021/09/20
- [PULL 27/27] target/arm: Optimize MVE 1op-immediate insns, Peter Maydell, 2021/09/20
- [PULL 23/27] target/arm: Optimize MVE VMVN,
Peter Maydell <=