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[PULL 17/27] target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound mig
From: |
Peter Maydell |
Subject: |
[PULL 17/27] target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration |
Date: |
Mon, 20 Sep 2021 15:19:37 +0100 |
Architecturally, for an M-profile CPU with the LOB feature the
LTPSIZE field in FPDSCR is always constant 4. QEMU's implementation
enforces this everywhere, except that we don't check that it is true
in incoming migration data.
We're going to add come in gen_update_fp_context() which relies on
the "always 4" property. Since this is TCG-only, we don't actually
need to be robust to bogus incoming migration data, and the effect of
it being wrong would be wrong code generation rather than a QEMU
crash; but if it did ever happen somehow it would be very difficult
to track down the cause. Add a check so that we fail the inbound
migration if the FPDSCR.LTPSIZE value is incorrect.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-3-peter.maydell@linaro.org
---
target/arm/machine.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 81e30de8243..c74d8c3f4b3 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -781,6 +781,19 @@ static int cpu_post_load(void *opaque, int version_id)
hw_breakpoint_update_all(cpu);
hw_watchpoint_update_all(cpu);
+ /*
+ * TCG gen_update_fp_context() relies on the invariant that
+ * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension;
+ * forbid bogus incoming data with some other value.
+ */
+ if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)) {
+ if (extract32(env->v7m.fpdscr[M_REG_NS],
+ FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4 ||
+ extract32(env->v7m.fpdscr[M_REG_S],
+ FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4) {
+ return -1;
+ }
+ }
if (!kvm_enabled()) {
pmu_op_finish(&cpu->env);
}
--
2.20.1
- [PULL 05/27] target/arm: Consolidate ifdef blocks in reset, (continued)
- [PULL 05/27] target/arm: Consolidate ifdef blocks in reset, Peter Maydell, 2021/09/20
- [PULL 11/27] arm/hvf: Add a WFI handler, Peter Maydell, 2021/09/20
- [PULL 13/27] hvf: arm: Implement PSCI handling, Peter Maydell, 2021/09/20
- [PULL 15/27] hvf: arm: Add rudimentary PMC support, Peter Maydell, 2021/09/20
- [PULL 20/27] target/arm: Optimize MVE arithmetic ops, Peter Maydell, 2021/09/20
- [PULL 21/27] target/arm: Optimize MVE VNEG, VABS, Peter Maydell, 2021/09/20
- [PULL 24/27] target/arm: Optimize MVE VSHL, VSHR immediate forms, Peter Maydell, 2021/09/20
- [PULL 16/27] target/arm: Avoid goto_tb if we're trying to exit to the main loop, Peter Maydell, 2021/09/20
- [PULL 26/27] target/arm: Optimize MVE VSLI and VSRI, Peter Maydell, 2021/09/20
- [PULL 19/27] target/arm: Optimize MVE logic ops, Peter Maydell, 2021/09/20
- [PULL 17/27] target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration,
Peter Maydell <=
- [PULL 22/27] target/arm: Optimize MVE VDUP, Peter Maydell, 2021/09/20
- [PULL 25/27] target/arm: Optimize MVE VSHLL and VMOVL, Peter Maydell, 2021/09/20
- [PULL 02/27] elf2dmp: Fail cleanly if PDB file specifies zero block_size, Peter Maydell, 2021/09/20
- [PULL 14/27] arm: Add Hypervisor.framework build target, Peter Maydell, 2021/09/20
- [PULL 18/27] target/arm: Add TB flag for "MVE insns not predicated", Peter Maydell, 2021/09/20
- [PULL 27/27] target/arm: Optimize MVE 1op-immediate insns, Peter Maydell, 2021/09/20
- [PULL 23/27] target/arm: Optimize MVE VMVN, Peter Maydell, 2021/09/20