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[PULL 21/27] target/arm: Optimize MVE VNEG, VABS
From: |
Peter Maydell |
Subject: |
[PULL 21/27] target/arm: Optimize MVE VNEG, VABS |
Date: |
Mon, 20 Sep 2021 15:19:41 +0100 |
Optimize the MVE VNEG and VABS insns by using TCG
vector ops when possible.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-7-peter.maydell@linaro.org
---
target/arm/translate-mve.c | 32 ++++++++++++++++++++++----------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 255cb860fec..d30c7e57ea3 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -510,7 +510,8 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
return true;
}
-static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
+static bool do_1op_vec(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn,
+ GVecGen2Fn vecfn)
{
TCGv_ptr qd, qm;
@@ -524,16 +525,25 @@ static bool do_1op(DisasContext *s, arg_1op *a,
MVEGenOneOpFn fn)
return true;
}
- qd = mve_qreg_ptr(a->qd);
- qm = mve_qreg_ptr(a->qm);
- fn(cpu_env, qd, qm);
- tcg_temp_free_ptr(qd);
- tcg_temp_free_ptr(qm);
+ if (vecfn && mve_no_predication(s)) {
+ vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qm), 16, 16);
+ } else {
+ qd = mve_qreg_ptr(a->qd);
+ qm = mve_qreg_ptr(a->qm);
+ fn(cpu_env, qd, qm);
+ tcg_temp_free_ptr(qd);
+ tcg_temp_free_ptr(qm);
+ }
mve_update_eci(s);
return true;
}
-#define DO_1OP(INSN, FN) \
+static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
+{
+ return do_1op_vec(s, a, fn, NULL);
+}
+
+#define DO_1OP_VEC(INSN, FN, VECFN) \
static bool trans_##INSN(DisasContext *s, arg_1op *a) \
{ \
static MVEGenOneOpFn * const fns[] = { \
@@ -542,13 +552,15 @@ static bool do_1op(DisasContext *s, arg_1op *a,
MVEGenOneOpFn fn)
gen_helper_mve_##FN##w, \
NULL, \
}; \
- return do_1op(s, a, fns[a->size]); \
+ return do_1op_vec(s, a, fns[a->size], VECFN); \
}
+#define DO_1OP(INSN, FN) DO_1OP_VEC(INSN, FN, NULL)
+
DO_1OP(VCLZ, vclz)
DO_1OP(VCLS, vcls)
-DO_1OP(VABS, vabs)
-DO_1OP(VNEG, vneg)
+DO_1OP_VEC(VABS, vabs, tcg_gen_gvec_abs)
+DO_1OP_VEC(VNEG, vneg, tcg_gen_gvec_neg)
DO_1OP(VQABS, vqabs)
DO_1OP(VQNEG, vqneg)
DO_1OP(VMAXA, vmaxa)
--
2.20.1
- [PULL 12/27] hvf: arm: Implement -cpu host, (continued)
- [PULL 12/27] hvf: arm: Implement -cpu host, Peter Maydell, 2021/09/20
- [PULL 10/27] hvf: Add Apple Silicon support, Peter Maydell, 2021/09/20
- [PULL 01/27] elf2dmp: Check curl_easy_setopt() return value, Peter Maydell, 2021/09/20
- [PULL 09/27] hvf: Introduce hvf_arch_init() callback, Peter Maydell, 2021/09/20
- [PULL 08/27] hvf: Add execute to dirty log permission bitmap, Peter Maydell, 2021/09/20
- [PULL 05/27] target/arm: Consolidate ifdef blocks in reset, Peter Maydell, 2021/09/20
- [PULL 11/27] arm/hvf: Add a WFI handler, Peter Maydell, 2021/09/20
- [PULL 13/27] hvf: arm: Implement PSCI handling, Peter Maydell, 2021/09/20
- [PULL 15/27] hvf: arm: Add rudimentary PMC support, Peter Maydell, 2021/09/20
- [PULL 20/27] target/arm: Optimize MVE arithmetic ops, Peter Maydell, 2021/09/20
- [PULL 21/27] target/arm: Optimize MVE VNEG, VABS,
Peter Maydell <=
- [PULL 24/27] target/arm: Optimize MVE VSHL, VSHR immediate forms, Peter Maydell, 2021/09/20
- [PULL 16/27] target/arm: Avoid goto_tb if we're trying to exit to the main loop, Peter Maydell, 2021/09/20
- [PULL 26/27] target/arm: Optimize MVE VSLI and VSRI, Peter Maydell, 2021/09/20
- [PULL 19/27] target/arm: Optimize MVE logic ops, Peter Maydell, 2021/09/20
- [PULL 17/27] target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration, Peter Maydell, 2021/09/20
- [PULL 22/27] target/arm: Optimize MVE VDUP, Peter Maydell, 2021/09/20
- [PULL 25/27] target/arm: Optimize MVE VSHLL and VMOVL, Peter Maydell, 2021/09/20
- [PULL 02/27] elf2dmp: Fail cleanly if PDB file specifies zero block_size, Peter Maydell, 2021/09/20
- [PULL 14/27] arm: Add Hypervisor.framework build target, Peter Maydell, 2021/09/20
- [PULL 18/27] target/arm: Add TB flag for "MVE insns not predicated", Peter Maydell, 2021/09/20