Re: [PATCH v3 03/30] tcg/loongarch64: Add the tcg-target.h file

[Philippe Mathieu-Daudé]

On 9/22/21 20:09, WANG Xuerui wrote:
> Support for all optional TCG ops are initially marked disabled; the bits
> are to be set in individual commits later.
>
> Signed-off-by: WANG Xuerui <git@xen0n.name>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   tcg/loongarch64/tcg-target.h | 180 +++++++++++++++++++++++++++++++++++
>   1 file changed, 180 insertions(+)
>   create mode 100644 tcg/loongarch64/tcg-target.h
>
> diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
> new file mode 100644
> index 0000000000..0fd9b61e6d
> --- /dev/null
> +++ b/tcg/loongarch64/tcg-target.h
> @@ -0,0 +1,180 @@
> +/*
> + * Tiny Code Generator for QEMU
> + *
> + * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
> + *
> + * Based on tcg/riscv/tcg-target.h
> + *
> + * Copyright (c) 2018 SiFive, Inc

I thought you could drop this line.

> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to 
> deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef LOONGARCH_TCG_TARGET_H
> +#define LOONGARCH_TCG_TARGET_H
> +
> +/*
> + * Loongson removed the (incomplete) 32-bit support from kernel and toolchain
> + * for the initial upstreaming of this architecture, so don't bother and just
> + * support the LP64 ABI for now.
> + */
> +#if defined(__loongarch64)
> +# define TCG_TARGET_REG_BITS 64
> +#else
> +# error unsupported LoongArch register size
> +#endif
> +
> +#define TCG_TARGET_INSN_UNIT_SIZE 4
> +#define TCG_TARGET_NB_REGS 32
> +#define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)

Is this SIZE_MAX?

> +
> +typedef enum {
> +    TCG_REG_ZERO,
> +    TCG_REG_RA,
> +    TCG_REG_TP,
> +    TCG_REG_SP,
> +    TCG_REG_A0,
> +    TCG_REG_A1,
> +    TCG_REG_A2,
> +    TCG_REG_A3,
> +    TCG_REG_A4,
> +    TCG_REG_A5,
> +    TCG_REG_A6,
> +    TCG_REG_A7,
> +    TCG_REG_T0,
> +    TCG_REG_T1,
> +    TCG_REG_T2,
> +    TCG_REG_T3,
> +    TCG_REG_T4,
> +    TCG_REG_T5,
> +    TCG_REG_T6,
> +    TCG_REG_T7,
> +    TCG_REG_T8,
> +    TCG_REG_RESERVED,
> +    TCG_REG_S9,
> +    TCG_REG_S0,
> +    TCG_REG_S1,
> +    TCG_REG_S2,
> +    TCG_REG_S3,
> +    TCG_REG_S4,
> +    TCG_REG_S5,
> +    TCG_REG_S6,
> +    TCG_REG_S7,
> +    TCG_REG_S8,

Here could go:

       TCG_TARGET_NB_REGS,

> +
> +    /* aliases */
> +    TCG_AREG0    = TCG_REG_S0,
> +    TCG_REG_TMP0 = TCG_REG_T8,
> +    TCG_REG_TMP1 = TCG_REG_T7,
> +    TCG_REG_TMP2 = TCG_REG_T6,
> +} TCGReg;

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>