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[PULL 01/22] allwinner-h3: Switch to SMC as PSCI conduit
From: |
Peter Maydell |
Subject: |
[PULL 01/22] allwinner-h3: Switch to SMC as PSCI conduit |
Date: |
Thu, 30 Sep 2021 16:11:40 +0100 |
From: Alexander Graf <agraf@csgraf.de>
The Allwinner H3 SoC uses Cortex-A7 cores which support virtualization.
However, today we are configuring QEMU to use HVC as PSCI conduit.
That means HVC calls get trapped into QEMU instead of the guest's own
emulated CPU and thus break the guest's ability to execute virtualization.
Fix this by moving to SMC as conduit, freeing up HYP completely to the VM.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Message-id: 20210920203931.66527-1-agraf@csgraf.de
Fixes: 740dafc0ba0 ("hw/arm: add Allwinner H3 System-on-Chip")
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/allwinner-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 27f10701453..f9b7ed18711 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -237,7 +237,7 @@ static void allwinner_h3_realize(DeviceState *dev, Error
**errp)
/* Provide Power State Coordination Interface */
qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
- QEMU_PSCI_CONDUIT_HVC);
+ QEMU_PSCI_CONDUIT_SMC);
/* Disable secondary CPUs */
qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
--
2.20.1
- [PULL 00/22] target-arm queue, Peter Maydell, 2021/09/30
- [PULL 01/22] allwinner-h3: Switch to SMC as PSCI conduit,
Peter Maydell <=
- [PULL 02/22] arm: tcg: Adhere to SMCCC 1.3 section 5.2, Peter Maydell, 2021/09/30
- [PULL 03/22] hw/nvram: Introduce Xilinx eFuse QOM, Peter Maydell, 2021/09/30
- [PULL 05/22] hw/nvram: Introduce Xilinx ZynqMP eFuse device, Peter Maydell, 2021/09/30
- [PULL 04/22] hw/nvram: Introduce Xilinx Versal eFuse device, Peter Maydell, 2021/09/30
- [PULL 10/22] hw/arm: xlnx-zcu102: Add Xilinx eFUSE device, Peter Maydell, 2021/09/30
- [PULL 12/22] configs: Don't include 32-bit-only GDB XML in aarch64 linux configs, Peter Maydell, 2021/09/30
- [PULL 09/22] hw/arm: xlnx-zcu102: Add Xilinx BBRAM device, Peter Maydell, 2021/09/30
- [PULL 06/22] hw/nvram: Introduce Xilinx battery-backed ram, Peter Maydell, 2021/09/30
- [PULL 07/22] hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device, Peter Maydell, 2021/09/30
- [PULL 08/22] hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device, Peter Maydell, 2021/09/30