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[PULL 02/22] arm: tcg: Adhere to SMCCC 1.3 section 5.2
From: |
Peter Maydell |
Subject: |
[PULL 02/22] arm: tcg: Adhere to SMCCC 1.3 section 5.2 |
Date: |
Thu, 30 Sep 2021 16:11:41 +0100 |
From: Alexander Graf <agraf@csgraf.de>
The SMCCC 1.3 spec section 5.2 says
The Unknown SMC Function Identifier is a sign-extended value of (-1)
that is returned in the R0, W0 or X0 registers. An implementation must
return this error code when it receives:
* An SMC or HVC call with an unknown Function Identifier
* An SMC or HVC call for a removed Function Identifier
* An SMC64/HVC64 call from AArch32 state
To comply with these statements, let's always return -1 when we encounter
an unknown HVC or SMC call.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/psci.c | 35 ++++++-----------------------------
1 file changed, 6 insertions(+), 29 deletions(-)
diff --git a/target/arm/psci.c b/target/arm/psci.c
index 6709e280133..b279c0b9a45 100644
--- a/target/arm/psci.c
+++ b/target/arm/psci.c
@@ -27,15 +27,13 @@
bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
{
- /* Return true if the r0/x0 value indicates a PSCI call and
- * the exception type matches the configured PSCI conduit. This is
- * called before the SMC/HVC instruction is executed, to decide whether
- * we should treat it as a PSCI call or with the architecturally
+ /*
+ * Return true if the exception type matches the configured PSCI conduit.
+ * This is called before the SMC/HVC instruction is executed, to decide
+ * whether we should treat it as a PSCI call or with the architecturally
* defined behaviour for an SMC or HVC (which might be UNDEF or trap
* to EL2 or to EL3).
*/
- CPUARMState *env = &cpu->env;
- uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];
switch (excp_type) {
case EXCP_HVC:
@@ -52,27 +50,7 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
return false;
}
- switch (param) {
- case QEMU_PSCI_0_2_FN_PSCI_VERSION:
- case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
- case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
- case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
- case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
- case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
- case QEMU_PSCI_0_1_FN_CPU_ON:
- case QEMU_PSCI_0_2_FN_CPU_ON:
- case QEMU_PSCI_0_2_FN64_CPU_ON:
- case QEMU_PSCI_0_1_FN_CPU_OFF:
- case QEMU_PSCI_0_2_FN_CPU_OFF:
- case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
- case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
- case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
- case QEMU_PSCI_0_1_FN_MIGRATE:
- case QEMU_PSCI_0_2_FN_MIGRATE:
- return true;
- default:
- return false;
- }
+ return true;
}
void arm_handle_psci_call(ARMCPU *cpu)
@@ -194,10 +172,9 @@ void arm_handle_psci_call(ARMCPU *cpu)
break;
case QEMU_PSCI_0_1_FN_MIGRATE:
case QEMU_PSCI_0_2_FN_MIGRATE:
+ default:
ret = QEMU_PSCI_RET_NOT_SUPPORTED;
break;
- default:
- g_assert_not_reached();
}
err:
--
2.20.1
- [PULL 00/22] target-arm queue, Peter Maydell, 2021/09/30
- [PULL 01/22] allwinner-h3: Switch to SMC as PSCI conduit, Peter Maydell, 2021/09/30
- [PULL 02/22] arm: tcg: Adhere to SMCCC 1.3 section 5.2,
Peter Maydell <=
- [PULL 03/22] hw/nvram: Introduce Xilinx eFuse QOM, Peter Maydell, 2021/09/30
- [PULL 05/22] hw/nvram: Introduce Xilinx ZynqMP eFuse device, Peter Maydell, 2021/09/30
- [PULL 04/22] hw/nvram: Introduce Xilinx Versal eFuse device, Peter Maydell, 2021/09/30
- [PULL 10/22] hw/arm: xlnx-zcu102: Add Xilinx eFUSE device, Peter Maydell, 2021/09/30
- [PULL 12/22] configs: Don't include 32-bit-only GDB XML in aarch64 linux configs, Peter Maydell, 2021/09/30
- [PULL 09/22] hw/arm: xlnx-zcu102: Add Xilinx BBRAM device, Peter Maydell, 2021/09/30
- [PULL 06/22] hw/nvram: Introduce Xilinx battery-backed ram, Peter Maydell, 2021/09/30
- [PULL 07/22] hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device, Peter Maydell, 2021/09/30
- [PULL 08/22] hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device, Peter Maydell, 2021/09/30
- [PULL 11/22] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage, Peter Maydell, 2021/09/30