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[PATCH v4 32/45] target/arm: Enable FEAT_Debugv8p4 for -cpu max
From: |
Richard Henderson |
Subject: |
[PATCH v4 32/45] target/arm: Enable FEAT_Debugv8p4 for -cpu max |
Date: |
Sat, 30 Apr 2022 22:50:14 -0700 |
This extension concerns changes to the External Debug interface,
with Secure and Non-secure access to the debug registers, and all
of it is outside the scope of QEMU. Indicating support for this
is mandatory with FEAT_SEL2, which we do implement.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c | 2 +-
target/arm/cpu_tcg.c | 4 ++--
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 965f35d8c9..0acac6347c 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -15,6 +15,7 @@ the following architecture extensions:
- FEAT_DIT (Data Independent Timing instructions)
- FEAT_DPB (DC CVAP instruction)
- FEAT_Debugv8p2 (Debug changes for v8.2)
+- FEAT_Debugv8p4 (Debug changes for v8.4)
- FEAT_DotProd (Advanced SIMD dot product instructions)
- FEAT_FCMA (Floating-point complex number instructions)
- FEAT_FHM (Floating-point half-precision multiplication instructions)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 202fd5c46e..88d3cef93e 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -799,7 +799,7 @@ static void aarch64_max_initfn(Object *obj)
cpu->isar.id_aa64zfr0 = t;
t = cpu->isar.id_aa64dfr0;
- t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
cpu->isar.id_aa64dfr0 = t;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index b6fc3752f2..337598e949 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -76,8 +76,8 @@ void aa32_max_features(ARMCPU *cpu)
cpu->isar.id_pfr2 = t;
t = cpu->isar.id_dfr0;
- t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */
- t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
cpu->isar.id_dfr0 = t;
}
--
2.34.1
- Re: [PATCH v4 20/45] target/arm: Handle cpreg registration for missing EL, (continued)
[PATCH v4 21/45] target/arm: Drop EL3 no EL2 fallbacks, Richard Henderson, 2022/05/01
[PATCH v4 15/45] target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable, Richard Henderson, 2022/05/01
[PATCH v4 25/45] target/arm: Move cortex impdef sysregs to cpu_tcg.c, Richard Henderson, 2022/05/01
[PATCH v4 11/45] target/arm: Store cpregs key in the hash table directly, Richard Henderson, 2022/05/01
[PATCH v4 30/45] target/arm: Use field names for manipulating EL2 and EL3 modes, Richard Henderson, 2022/05/01
[PATCH v4 32/45] target/arm: Enable FEAT_Debugv8p4 for -cpu max,
Richard Henderson <=
[PATCH v4 09/45] target/arm: Name CPSecureState type, Richard Henderson, 2022/05/01
[PATCH v4 08/45] target/arm: Name CPState type, Richard Henderson, 2022/05/01
[PATCH v4 16/45] target/arm: Hoist isbanked computation in add_cpreg_to_hashtable, Richard Henderson, 2022/05/01
[PATCH v4 13/45] target/arm: Hoist computation of key in add_cpreg_to_hashtable, Richard Henderson, 2022/05/01
[PATCH v4 17/45] target/arm: Perform override check early in add_cpreg_to_hashtable, Richard Henderson, 2022/05/01
[PATCH v4 26/45] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Richard Henderson, 2022/05/01
[PATCH v4 12/45] target/arm: Merge allocation of the cpreg and its name, Richard Henderson, 2022/05/01