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[PATCH v4 09/45] target/arm: Name CPSecureState type
From: |
Richard Henderson |
Subject: |
[PATCH v4 09/45] target/arm: Name CPSecureState type |
Date: |
Sat, 30 Apr 2022 22:49:51 -0700 |
Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable.
Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0
is handled in define_one_arm_cp_reg_with_opaque.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpregs.h | 7 ++++---
target/arm/helper.c | 7 +++++--
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 4179a8cdd5..73984549d2 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -131,10 +131,11 @@ typedef enum {
* registered entry will only have one to identify whether the entry is secure
* or non-secure.
*/
-enum {
+typedef enum {
+ ARM_CP_SECSTATE_BOTH = 0, /* define one cpreg for each secstate */
ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
-};
+} CPSecureState;
/*
* Access rights:
@@ -266,7 +267,7 @@ struct ARMCPRegInfo {
/* Access rights: PL*_[RW] */
CPAccessRights access;
/* Security state: ARM_CP_SECSTATE_* bits/values */
- int secure;
+ CPSecureState secure;
/*
* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
* this register was defined: can be used to hand data through to the
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d560a6a6a9..50ad2e3e37 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8502,7 +8502,8 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error
**errp)
}
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
- void *opaque, CPState state, int secstate,
+ void *opaque, CPState state,
+ CPSecureState secstate,
int crm, int opc1, int opc2,
const char *name)
{
@@ -8785,7 +8786,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
r->secure, crm, opc1, opc2,
r->name);
break;
- default:
+ case ARM_CP_SECSTATE_BOTH:
name = g_strdup_printf("%s_S", r->name);
add_cpreg_to_hashtable(cpu, r, opaque, state,
ARM_CP_SECSTATE_S,
@@ -8795,6 +8796,8 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
ARM_CP_SECSTATE_NS,
crm, opc1, opc2, r->name);
break;
+ default:
+ g_assert_not_reached();
}
} else {
/* AArch64 registers get mapped to non-secure instance
--
2.34.1
- Re: [PATCH v4 20/45] target/arm: Handle cpreg registration for missing EL, (continued)
- [PATCH v4 21/45] target/arm: Drop EL3 no EL2 fallbacks, Richard Henderson, 2022/05/01
- [PATCH v4 15/45] target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable, Richard Henderson, 2022/05/01
- [PATCH v4 25/45] target/arm: Move cortex impdef sysregs to cpu_tcg.c, Richard Henderson, 2022/05/01
- [PATCH v4 11/45] target/arm: Store cpregs key in the hash table directly, Richard Henderson, 2022/05/01
- [PATCH v4 30/45] target/arm: Use field names for manipulating EL2 and EL3 modes, Richard Henderson, 2022/05/01
- [PATCH v4 32/45] target/arm: Enable FEAT_Debugv8p4 for -cpu max, Richard Henderson, 2022/05/01
- [PATCH v4 09/45] target/arm: Name CPSecureState type,
Richard Henderson <=
- [PATCH v4 08/45] target/arm: Name CPState type, Richard Henderson, 2022/05/01
- [PATCH v4 16/45] target/arm: Hoist isbanked computation in add_cpreg_to_hashtable, Richard Henderson, 2022/05/01
- [PATCH v4 13/45] target/arm: Hoist computation of key in add_cpreg_to_hashtable, Richard Henderson, 2022/05/01
- [PATCH v4 17/45] target/arm: Perform override check early in add_cpreg_to_hashtable, Richard Henderson, 2022/05/01
- [PATCH v4 26/45] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Richard Henderson, 2022/05/01
- [PATCH v4 12/45] target/arm: Merge allocation of the cpreg and its name, Richard Henderson, 2022/05/01