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[PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max
From: |
Peter Maydell |
Subject: |
[PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max |
Date: |
Mon, 9 May 2022 12:58:34 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c | 1 +
target/arm/cpu_tcg.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 0acac6347c5..81104080003 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -42,6 +42,7 @@ the following architecture extensions:
- FEAT_PMULL (PMULL, PMULL2 instructions)
- FEAT_PMUv3p1 (PMU Extensions v3.1)
- FEAT_PMUv3p4 (PMU Extensions v3.4)
+- FEAT_RAS (Reliability, availability, and serviceability)
- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
- FEAT_RNG (Random number generator)
- FEAT_SB (Speculation Barrier)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 88d3cef93e8..35881c74b20 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -744,6 +744,7 @@ static void aarch64_max_initfn(Object *obj)
t = cpu->isar.id_aa64pfr0;
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
+ t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 337598e9490..c5cf7efe95c 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -69,6 +69,7 @@ void aa32_max_features(ARMCPU *cpu)
t = cpu->isar.id_pfr0;
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
+ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
cpu->isar.id_pfr0 = t;
t = cpu->isar.id_pfr2;
--
2.25.1
- [PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers, (continued)
- [PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers, Peter Maydell, 2022/05/09
- [PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes, Peter Maydell, 2022/05/09
- [PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Peter Maydell, 2022/05/09
- [PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Peter Maydell, 2022/05/09
- [PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max, Peter Maydell, 2022/05/09
- [PULL 15/32] target/arm: Enable SCR and HCR bits for RAS, Peter Maydell, 2022/05/09
- [PULL 17/32] target/arm: Implement ESB instruction, Peter Maydell, 2022/05/09
- [PULL 16/32] target/arm: Implement virtual SError exceptions, Peter Maydell, 2022/05/09
- [PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max, Peter Maydell, 2022/05/09
- [PULL 20/32] target/arm: Enable FEAT_CSV2 for -cpu max, Peter Maydell, 2022/05/09
- [PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max,
Peter Maydell <=
- [PULL 21/32] target/arm: Enable FEAT_CSV2_2 for -cpu max, Peter Maydell, 2022/05/09
- [PULL 22/32] target/arm: Enable FEAT_CSV3 for -cpu max, Peter Maydell, 2022/05/09
- [PULL 24/32] target/arm: Define cortex-a76, Peter Maydell, 2022/05/09
- [PULL 23/32] target/arm: Enable FEAT_DGH for -cpu max, Peter Maydell, 2022/05/09
- [PULL 13/32] target/arm: Enable FEAT_Debugv8p4 for -cpu max, Peter Maydell, 2022/05/09
- [PULL 27/32] qapi/machine.json: Add cluster-id, Peter Maydell, 2022/05/09
- [PULL 25/32] target/arm: Define neoverse-n1, Peter Maydell, 2022/05/09
- [PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu(), Peter Maydell, 2022/05/09
- [PULL 26/32] hw/arm: add versioning to sbsa-ref machine DT, Peter Maydell, 2022/05/09
- [PULL 14/32] target/arm: Add minimal RAS registers, Peter Maydell, 2022/05/09