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[PULL 17/91] qtest/cxl: Introduce initial test for pxb-cxl only.
From: |
Michael S. Tsirkin |
Subject: |
[PULL 17/91] qtest/cxl: Introduce initial test for pxb-cxl only. |
Date: |
Mon, 16 May 2022 06:36:33 -0400 |
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Initial test with just pxb-cxl. Other tests will be added
alongside functionality.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-16-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/cxl-test.c | 22 ++++++++++++++++++++++
tests/qtest/meson.build | 4 ++++
2 files changed, 26 insertions(+)
create mode 100644 tests/qtest/cxl-test.c
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
new file mode 100644
index 0000000000..c031049930
--- /dev/null
+++ b/tests/qtest/cxl-test.c
@@ -0,0 +1,22 @@
+/*
+ * QTest testcase for CXL
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest-single.h"
+
+static void cxl_basic_pxb(void)
+{
+ qtest_start("-machine q35,cxl=on -device pxb-cxl,bus=pcie.0");
+ qtest_end();
+}
+
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+ qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb);
+ return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 3551b9c946..71e86bc2a3 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -35,6 +35,9 @@ qtests_pci = \
(config_all_devices.has_key('CONFIG_VGA') ? ['display-vga-test'] : []) +
\
(config_all_devices.has_key('CONFIG_IVSHMEM_DEVICE') ? ['ivshmem-test'] : [])
+qtests_cxl = \
+ (config_all_devices.has_key('CONFIG_CXL') ? ['cxl-test'] : [])
+
qtests_i386 = \
(slirp.found() ? ['pxe-test', 'test-netfilter'] : []) + \
(config_host.has_key('CONFIG_POSIX') ? ['test-filter-mirror'] : []) +
\
@@ -74,6 +77,7 @@ qtests_i386 = \
slirp.found() ? ['virtio-net-failover'] : []) +
\
(unpack_edk2_blobs ? ['bios-tables-test'] : []) +
\
qtests_pci +
\
+ qtests_cxl +
\
['fdc-test',
'ide-test',
'hd-geo-test',
--
MST
- [PULL 07/91] hw/cxl/device: Implement the CAP array (8.2.8.1-2), (continued)
- [PULL 07/91] hw/cxl/device: Implement the CAP array (8.2.8.1-2), Michael S. Tsirkin, 2022/05/16
- [PULL 08/91] hw/cxl/device: Implement basic mailbox (8.2.8.4), Michael S. Tsirkin, 2022/05/16
- [PULL 06/91] hw/cxl/device: Introduce a CXL device (8.2.8), Michael S. Tsirkin, 2022/05/16
- [PULL 09/91] hw/cxl/device: Add memory device utilities, Michael S. Tsirkin, 2022/05/16
- [PULL 11/91] hw/cxl/device: Timestamp implementation (8.2.9.3), Michael S. Tsirkin, 2022/05/16
- [PULL 10/91] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1), Michael S. Tsirkin, 2022/05/16
- [PULL 12/91] hw/cxl/device: Add log commands (8.2.9.4) + CEL, Michael S. Tsirkin, 2022/05/16
- [PULL 13/91] hw/pxb: Use a type for realizing expanders, Michael S. Tsirkin, 2022/05/16
- [PULL 14/91] hw/pci/cxl: Create a CXL bus type, Michael S. Tsirkin, 2022/05/16
- [PULL 15/91] cxl: Machine level control on whether CXL support is enabled, Michael S. Tsirkin, 2022/05/16
- [PULL 17/91] qtest/cxl: Introduce initial test for pxb-cxl only.,
Michael S. Tsirkin <=
- [PULL 16/91] hw/pxb: Allow creation of a CXL PXB (host bridge), Michael S. Tsirkin, 2022/05/16
- [PULL 18/91] hw/cxl/rp: Add a root port, Michael S. Tsirkin, 2022/05/16
- [PULL 19/91] hw/cxl/device: Add a memory device (8.2.8.5), Michael S. Tsirkin, 2022/05/16
- [PULL 20/91] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12), Michael S. Tsirkin, 2022/05/16
- [PULL 21/91] hw/cxl/device: Add some trivial commands, Michael S. Tsirkin, 2022/05/16
- [PULL 22/91] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing, Michael S. Tsirkin, 2022/05/16
- [PULL 23/91] hw/cxl/device: Implement get/set Label Storage Area (LSA), Michael S. Tsirkin, 2022/05/16
- [PULL 24/91] qtests/cxl: Add initial root port and CXL type3 tests, Michael S. Tsirkin, 2022/05/16
- [PULL 25/91] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), Michael S. Tsirkin, 2022/05/16
- [PULL 26/91] acpi/cxl: Add _OSC implementation (9.14.2), Michael S. Tsirkin, 2022/05/16