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[PULL 07/22] hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GIC
From: |
Peter Maydell |
Subject: |
[PULL 07/22] hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters |
Date: |
Thu, 19 May 2022 18:36:36 +0100 |
We allow a GICv3 to be connected to any CPU, but we don't do anything
to handle the case where the CPU type doesn't in hardware have a
GICv3 CPU interface and so the various GIC configuration fields
(gic_num_lrs, vprebits, vpribits) are not specified.
The current behaviour is that we will add the EL1 CPU interface
registers, but will not put in the EL2 CPU interface registers, even
if the CPU has EL2, which will leave the GIC in a broken state and
probably result in the guest crashing as it tries to set it up. This
only affects the virt board when using the cortex-a15 or cortex-a7
CPU types (both 32-bit) with -machine gic-version=3 (or 'max')
and -machine virtualization=on.
Instead of failing to set up the EL2 registers, if the CPU doesn't
define the GIC configuration set it to a reasonable default, matching
the standard configuration for most Arm CPUs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-2-peter.maydell@linaro.org
---
hw/intc/arm_gicv3_cpuif.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 9efba798f82..df2f8583564 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -2755,6 +2755,15 @@ void gicv3_init_cpuif(GICv3State *s)
ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
GICv3CPUState *cs = &s->cpu[i];
+ /*
+ * If the CPU doesn't define a GICv3 configuration, probably because
+ * in real hardware it doesn't have one, then we use default values
+ * matching the one used by most Arm CPUs. This applies to:
+ * cpu->gic_num_lrs
+ * cpu->gic_vpribits
+ * cpu->gic_vprebits
+ */
+
/* Note that we can't just use the GICv3CPUState as an opaque pointer
* in define_arm_cp_regs_with_opaque(), because when we're called back
* it might be with code translated by CPU 0 but run by CPU 1, in
@@ -2763,13 +2772,12 @@ void gicv3_init_cpuif(GICv3State *s)
* get back to the GICv3CPUState from the CPUARMState.
*/
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
- if (arm_feature(&cpu->env, ARM_FEATURE_EL2)
- && cpu->gic_num_lrs) {
+ if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
int j;
- cs->num_list_regs = cpu->gic_num_lrs;
- cs->vpribits = cpu->gic_vpribits;
- cs->vprebits = cpu->gic_vprebits;
+ cs->num_list_regs = cpu->gic_num_lrs ?: 4;
+ cs->vpribits = cpu->gic_vpribits ?: 5;
+ cs->vprebits = cpu->gic_vprebits ?: 5;
/* Check against architectural constraints: getting these
* wrong would be a bug in the CPU code defining these,
--
2.25.1
- [PULL 00/22] target-arm queue, Peter Maydell, 2022/05/19
- [PULL 03/22] target/arm: Implement FEAT_S2FWB, Peter Maydell, 2022/05/19
- [PULL 01/22] target/arm: Postpone interpretation of stage 2 descriptor attribute bits, Peter Maydell, 2022/05/19
- [PULL 05/22] target/arm: Implement FEAT_IDST, Peter Maydell, 2022/05/19
- [PULL 04/22] target/arm: Enable FEAT_S2FWB for -cpu max, Peter Maydell, 2022/05/19
- [PULL 07/22] hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters,
Peter Maydell <=
- [PULL 09/22] hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant, Peter Maydell, 2022/05/19
- [PULL 10/22] hw/intc/arm_gicv3: Support configurable number of physical priority bits, Peter Maydell, 2022/05/19
- [PULL 06/22] target/arm: Drop unsupported_encoding() macro, Peter Maydell, 2022/05/19
- [PULL 02/22] target/arm: Factor out FWB=0 specific part of combine_cacheattrs(), Peter Maydell, 2022/05/19
- [PULL 12/22] hw/intc/arm_gicv3: Provide ich_num_aprs(), Peter Maydell, 2022/05/19
- [PULL 11/22] hw/intc/arm_gicv3: Use correct number of priority bits for the CPU, Peter Maydell, 2022/05/19
- [PULL 14/22] hw/adc/zynq-xadc: Use qemu_irq typedef, Peter Maydell, 2022/05/19
- [PULL 15/22] target/arm/helper.c: Delete stray obsolete comment, Peter Maydell, 2022/05/19
- [PULL 13/22] Fix aarch64 debug register names., Peter Maydell, 2022/05/19
- [PULL 18/22] hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb node, Peter Maydell, 2022/05/19