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[PULL 12/22] hw/intc/arm_gicv3: Provide ich_num_aprs()
From: |
Peter Maydell |
Subject: |
[PULL 12/22] hw/intc/arm_gicv3: Provide ich_num_aprs() |
Date: |
Thu, 19 May 2022 18:36:41 +0100 |
We previously open-coded the expression for the number of virtual APR
registers and the assertion that it was not going to cause us to
overflow the cs->ich_apr[] array. Factor this out into a new
ich_num_aprs() function, for consistency with the icc_num_aprs()
function we just added for the physical APR handling.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-7-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-6-peter.maydell@linaro.org
---
hw/intc/arm_gicv3_cpuif.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 66e06b787c7..8867e2e496f 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -49,6 +49,14 @@ static inline int icv_min_vbpr(GICv3CPUState *cs)
return 7 - cs->vprebits;
}
+static inline int ich_num_aprs(GICv3CPUState *cs)
+{
+ /* Return the number of virtual APR registers (1, 2, or 4) */
+ int aprmax = 1 << (cs->vprebits - 5);
+ assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0]));
+ return aprmax;
+}
+
/* Simple accessor functions for LR fields */
static uint32_t ich_lr_vintid(uint64_t lr)
{
@@ -145,9 +153,7 @@ static int ich_highest_active_virt_prio(GICv3CPUState *cs)
* in the ICH Active Priority Registers.
*/
int i;
- int aprmax = 1 << (cs->vprebits - 5);
-
- assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0]));
+ int aprmax = ich_num_aprs(cs);
for (i = 0; i < aprmax; i++) {
uint32_t apr = cs->ich_apr[GICV3_G0][i] |
@@ -1333,9 +1339,7 @@ static int icv_drop_prio(GICv3CPUState *cs)
* 32 bits are actually relevant.
*/
int i;
- int aprmax = 1 << (cs->vprebits - 5);
-
- assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0]));
+ int aprmax = ich_num_aprs(cs);
for (i = 0; i < aprmax; i++) {
uint64_t *papr0 = &cs->ich_apr[GICV3_G0][i];
--
2.25.1
- [PULL 00/22] target-arm queue, Peter Maydell, 2022/05/19
- [PULL 03/22] target/arm: Implement FEAT_S2FWB, Peter Maydell, 2022/05/19
- [PULL 01/22] target/arm: Postpone interpretation of stage 2 descriptor attribute bits, Peter Maydell, 2022/05/19
- [PULL 05/22] target/arm: Implement FEAT_IDST, Peter Maydell, 2022/05/19
- [PULL 04/22] target/arm: Enable FEAT_S2FWB for -cpu max, Peter Maydell, 2022/05/19
- [PULL 07/22] hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters, Peter Maydell, 2022/05/19
- [PULL 09/22] hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant, Peter Maydell, 2022/05/19
- [PULL 10/22] hw/intc/arm_gicv3: Support configurable number of physical priority bits, Peter Maydell, 2022/05/19
- [PULL 06/22] target/arm: Drop unsupported_encoding() macro, Peter Maydell, 2022/05/19
- [PULL 02/22] target/arm: Factor out FWB=0 specific part of combine_cacheattrs(), Peter Maydell, 2022/05/19
- [PULL 12/22] hw/intc/arm_gicv3: Provide ich_num_aprs(),
Peter Maydell <=
- [PULL 11/22] hw/intc/arm_gicv3: Use correct number of priority bits for the CPU, Peter Maydell, 2022/05/19
- [PULL 14/22] hw/adc/zynq-xadc: Use qemu_irq typedef, Peter Maydell, 2022/05/19
- [PULL 15/22] target/arm/helper.c: Delete stray obsolete comment, Peter Maydell, 2022/05/19
- [PULL 13/22] Fix aarch64 debug register names., Peter Maydell, 2022/05/19
- [PULL 18/22] hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb node, Peter Maydell, 2022/05/19
- [PULL 19/22] ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY, Peter Maydell, 2022/05/19
- [PULL 20/22] target/arm: Fix PAuth keys access checks for disabled SEL2, Peter Maydell, 2022/05/19
- [PULL 17/22] hw/arm/virt: Fix incorrect non-secure flash dtb node name, Peter Maydell, 2022/05/19
- [PULL 21/22] target/arm: Enable FEAT_HCX for -cpu max, Peter Maydell, 2022/05/19
- [PULL 16/22] target/arm: Make number of counters in PMCR follow the CPU, Peter Maydell, 2022/05/19