Re: [PATCH v3 20/49] semihosting: Split out common_semi_has_synccache

[Richard Henderson]

On 5/23/22 05:51, Peter Maydell wrote:
> On Sat, 21 May 2022 at 01:04, Richard Henderson
> <richard.henderson@linaro.org> wrote:
> > We already have some larger ifdef blocks for ARM and RISCV;
> > split out a boolean test for SYS_SYNCCACHE.
> >
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> > ---
> >   semihosting/arm-compat-semi.c | 20 +++++++++++++-------
> >   1 file changed, 13 insertions(+), 7 deletions(-)
> >
> > diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
> > index 9ea985beee..c53cb1891f 100644
> > --- a/semihosting/arm-compat-semi.c
> > +++ b/semihosting/arm-compat-semi.c
> > @@ -224,6 +224,12 @@ static inline target_ulong 
> > common_semi_stack_bottom(CPUState *cs)
> >       CPUARMState *env = &cpu->env;
> >       return is_a64(env) ? env->xregs[31] : env->regs[13];
> >   }
> > +
> > +static inline bool common_semi_has_synccache(CPUArchState *env)
> > +{
> > +    /* Invalid for A32/T32. */
> > +    return !is_a64(env);
> > +}
>
> Condition seems to be inverted ?

Oops, yes.


r~