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[PULL 01/23] target/riscv: Fix VS mode hypervisor CSR access
From: |
Alistair Francis |
Subject: |
[PULL 01/23] target/riscv: Fix VS mode hypervisor CSR access |
Date: |
Wed, 25 May 2022 08:44:06 +1000 |
From: Dylan Reid <dylan@rivosinc.com>
VS mode access to hypervisor CSRs should generate virtual, not illegal,
instruction exceptions.
Don't return early and indicate an illegal instruction exception when
accessing a hypervisor CSR from VS mode. Instead, fall through to the
`hmode` predicate to return the correct virtual instruction exception.
Signed-off-by: Dylan Reid <dgreid@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220506165456.297058-1-dgreid@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3500e07f92..4ea7df02c9 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3141,13 +3141,13 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
#if !defined(CONFIG_USER_ONLY)
int effective_priv = env->priv;
- if (riscv_has_ext(env, RVH) &&
- env->priv == PRV_S &&
- !riscv_cpu_virt_enabled(env)) {
+ if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
/*
- * We are in S mode without virtualisation, therefore we are in HS
Mode.
+ * We are in either HS or VS mode.
* Add 1 to the effective privledge level to allow us to access the
- * Hypervisor CSRs.
+ * Hypervisor CSRs. The `hmode` predicate will determine if access
+ * should be allowed(HS) or if a virtual instruction exception should
be
+ * raised(VS).
*/
effective_priv++;
}
--
2.35.3
- [PULL 00/23] riscv-to-apply queue, Alistair Francis, 2022/05/24
- [PULL 01/23] target/riscv: Fix VS mode hypervisor CSR access,
Alistair Francis <=
- [PULL 02/23] target/riscv: rvv: Fix early exit condition for whole register load/store, Alistair Francis, 2022/05/24
- [PULL 03/23] hw/intc: Pass correct hartid while updating mtimecmp, Alistair Francis, 2022/05/24
- [PULL 04/23] target/riscv: Move Zhinx* extensions on ISA string, Alistair Francis, 2022/05/24
- [PULL 05/23] target/riscv: Add short-isa-string option, Alistair Francis, 2022/05/24
- [PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike), Alistair Francis, 2022/05/24
- [PULL 07/23] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan), Alistair Francis, 2022/05/24
- [PULL 08/23] target/riscv: Fix coding style on "G" expansion, Alistair Francis, 2022/05/24
- [PULL 09/23] target/riscv: Disable "G" by default, Alistair Francis, 2022/05/24
- [PULL 10/23] target/riscv: Change "G" expansion, Alistair Francis, 2022/05/24
- [PULL 13/23] hw/vfio/pci-quirks: Resolve redundant property getters, Alistair Francis, 2022/05/24