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[PULL 08/23] target/riscv: Fix coding style on "G" expansion
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From: |
Alistair Francis |
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Subject: |
[PULL 08/23] target/riscv: Fix coding style on "G" expansion |
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Date: |
Wed, 25 May 2022 08:44:13 +1000 |
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Because ext_? members are boolean variables, operator `&&' should be
used instead of `&'.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Message-Id:
<91633f8349253656dd08bc8dc36498a9c7538b10.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index dc93412395..e439716337 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -596,8 +596,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
- if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
- cpu->cfg.ext_a & cpu->cfg.ext_f &
+ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
+ cpu->cfg.ext_a && cpu->cfg.ext_f &&
cpu->cfg.ext_d)) {
warn_report("Setting G will also set IMAFD");
cpu->cfg.ext_i = true;
--
2.35.3
- [PULL 00/23] riscv-to-apply queue, Alistair Francis, 2022/05/24
- [PULL 01/23] target/riscv: Fix VS mode hypervisor CSR access, Alistair Francis, 2022/05/24
- [PULL 02/23] target/riscv: rvv: Fix early exit condition for whole register load/store, Alistair Francis, 2022/05/24
- [PULL 03/23] hw/intc: Pass correct hartid while updating mtimecmp, Alistair Francis, 2022/05/24
- [PULL 04/23] target/riscv: Move Zhinx* extensions on ISA string, Alistair Francis, 2022/05/24
- [PULL 05/23] target/riscv: Add short-isa-string option, Alistair Francis, 2022/05/24
- [PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike), Alistair Francis, 2022/05/24
- [PULL 07/23] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan), Alistair Francis, 2022/05/24
- [PULL 08/23] target/riscv: Fix coding style on "G" expansion,
Alistair Francis <=
- [PULL 09/23] target/riscv: Disable "G" by default, Alistair Francis, 2022/05/24
- [PULL 10/23] target/riscv: Change "G" expansion, Alistair Francis, 2022/05/24
- [PULL 13/23] hw/vfio/pci-quirks: Resolve redundant property getters, Alistair Francis, 2022/05/24
- [PULL 12/23] target/riscv: Move/refactor ISA extension checks, Alistair Francis, 2022/05/24
- [PULL 14/23] hw/riscv/sifive_u: Resolve redundant property accessors, Alistair Francis, 2022/05/24
- [PULL 15/23] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize, Alistair Francis, 2022/05/24
- [PULL 16/23] target/riscv: Fix typo of mimpid cpu option, Alistair Francis, 2022/05/24
- [PULL 17/23] target/riscv: Fix csr number based privilege checking, Alistair Francis, 2022/05/24
- [PULL 18/23] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode, Alistair Francis, 2022/05/24
- [PULL 19/23] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps, Alistair Francis, 2022/05/24