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[PATCH v1 10/40] i386/tdx: Integrate tdx_caps->xfam_fixed0/1 into tdx_cp
From: |
Xiaoyao Li |
Subject: |
[PATCH v1 10/40] i386/tdx: Integrate tdx_caps->xfam_fixed0/1 into tdx_cpuid_lookup |
Date: |
Tue, 2 Aug 2022 15:47:20 +0800 |
KVMM requires userspace to pass XFAM configuration via CPUID leaves 0xDs.
Convert tdx_caps->xfam_fixed0/1 into corresponding
tdx_cpuid_lookup[].tdx_fixed0/1 field of CPUID leaves 0xD. Thus the
requirement can applied naturally.
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
target/i386/cpu.c | 3 ---
target/i386/cpu.h | 3 +++
target/i386/kvm/tdx.c | 24 ++++++++++++++++++++++++
3 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 194b5a31afac..45652bb2fd7c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1418,9 +1418,6 @@ static const X86RegisterInfo32
x86_reg_info_32[CPU_NB_REGS32] = {
};
#undef REGISTER
-/* CPUID feature bits available in XSS */
-#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK)
-
ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
[XSTATE_FP_BIT] = {
/* x87 FP state component is always enabled if XSAVE is supported */
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index cc9da9fc4318..90f403aecd8b 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -583,6 +583,9 @@ typedef enum X86Seg {
XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
XSTATE_XTILE_CFG_MASK |
XSTATE_XTILE_DATA_MASK)
+/* CPUID feature bits available in XSS */
+#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK)
+
/* CPUID feature words */
typedef enum FeatureWord {
FEAT_1_EDX, /* CPUID[1].EDX */
diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
index d12b03fa05c9..dffaa533f899 100644
--- a/target/i386/kvm/tdx.c
+++ b/target/i386/kvm/tdx.c
@@ -395,6 +395,30 @@ static void update_tdx_cpuid_lookup_by_tdx_caps(void)
entry->tdx_fixed0 &= ~config;
entry->tdx_fixed1 &= ~config;
}
+
+ /*
+ * Because KVM gets XFAM settings via CPUID leaves 0xD, map
+ * tdx_caps->xfam_fixed{0, 1} into tdx_cpuid_lookup[].tdx_fixed{0, 1}.
+ *
+ * Then the enforment applies in tdx_get_configurable_cpuid() naturally.
+ */
+ tdx_cpuid_lookup[FEAT_XSAVE_XCR0_LO].tdx_fixed0 =
+ (uint32_t)~tdx_caps->xfam_fixed0 & CPUID_XSTATE_XCR0_MASK;
+ tdx_cpuid_lookup[FEAT_XSAVE_XCR0_LO].tdx_fixed1 =
+ (uint32_t)tdx_caps->xfam_fixed1 & CPUID_XSTATE_XCR0_MASK;
+ tdx_cpuid_lookup[FEAT_XSAVE_XCR0_HI].tdx_fixed0 =
+ (~tdx_caps->xfam_fixed0 & CPUID_XSTATE_XCR0_MASK) >> 32;
+ tdx_cpuid_lookup[FEAT_XSAVE_XCR0_HI].tdx_fixed1 =
+ (tdx_caps->xfam_fixed1 & CPUID_XSTATE_XCR0_MASK) >> 32;
+
+ tdx_cpuid_lookup[FEAT_XSAVE_XSS_LO].tdx_fixed0 =
+ (uint32_t)~tdx_caps->xfam_fixed0 & CPUID_XSTATE_XSS_MASK;
+ tdx_cpuid_lookup[FEAT_XSAVE_XSS_LO].tdx_fixed1 =
+ (uint32_t)tdx_caps->xfam_fixed1 & CPUID_XSTATE_XSS_MASK;
+ tdx_cpuid_lookup[FEAT_XSAVE_XSS_HI].tdx_fixed0 =
+ (~tdx_caps->xfam_fixed0 & CPUID_XSTATE_XSS_MASK) >> 32;
+ tdx_cpuid_lookup[FEAT_XSAVE_XSS_HI].tdx_fixed1 =
+ (tdx_caps->xfam_fixed1 & CPUID_XSTATE_XSS_MASK) >> 32;
}
int tdx_kvm_init(MachineState *ms, Error **errp)
--
2.27.0
- [PATCH v1 07/40] i386/tdx: Introduce is_tdx_vm() helper and cache tdx_guest object, (continued)
- [PATCH v1 07/40] i386/tdx: Introduce is_tdx_vm() helper and cache tdx_guest object, Xiaoyao Li, 2022/08/02
- [PATCH v1 08/40] i386/tdx: Adjust the supported CPUID based on TDX restrictions, Xiaoyao Li, 2022/08/02
- [PATCH v1 09/40] i386/tdx: Update tdx_fixed0/1 bits by tdx_caps.cpuid_config[], Xiaoyao Li, 2022/08/02
- [PATCH v1 12/40] i386/kvm: Move architectural CPUID leaf generation to separate helper, Xiaoyao Li, 2022/08/02
- [PATCH v1 10/40] i386/tdx: Integrate tdx_caps->xfam_fixed0/1 into tdx_cpuid_lookup,
Xiaoyao Li <=
- [PATCH v1 11/40] i386/tdx: Integrate tdx_caps->attrs_fixed0/1 to tdx_cpuid_lookup, Xiaoyao Li, 2022/08/02
- [PATCH v1 13/40] KVM: Introduce kvm_arch_pre_create_vcpu(), Xiaoyao Li, 2022/08/02
- [PATCH v1 14/40] i386/tdx: Initialize TDX before creating TD vcpus, Xiaoyao Li, 2022/08/02
- [PATCH v1 15/40] i386/tdx: Add property sept-ve-disable for tdx-guest object, Xiaoyao Li, 2022/08/02
- [PATCH v1 16/40] i386/tdx: Wire CPU features up with attributes of TD guest, Xiaoyao Li, 2022/08/02