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From: | Richard Henderson |
Subject: | Re: [PATCH] riscv: Make semihosting configurable for all privilege modes |
Date: | Fri, 12 Aug 2022 16:27:25 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 |
On 8/11/22 13:41, Furquan Shaikh wrote:
Unlike ARM, RISC-V does not define a separate breakpoint type for semihosting. Instead, it is entirely ABI. Thus, we need an option to allow users to configure what the ebreak behavior should be for different privilege levels - M, S, U, VS, VU. As per the RISC-V privilege specification[1], ebreak traps into the execution environment. However, RISC-V debug specification[2] provides ebreak{m,s,u,vs,vu} configuration bits to allow ebreak behavior to be configured to trap into debug mode instead. This change adds settable properties for RISC-V CPUs - `ebreakm`, `ebreaks`, `ebreaku`, `ebreakvs` and `ebreakvu` to allow user to configure whether qemu should treat ebreak as semihosting traps or trap according to the privilege specification. [1] https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-privileged.pdf [2] https://github.com/riscv/riscv-debug-spec/blob/release/riscv-debug-release.pdf
I don't see why you need to change anything at all. Semihosting doesn't only use 'ebreak', but a sequence of 3 insns: slli x0, x0, 0x1f # 0x01f01013 Entry NOP ebreak # 0x00100073 Break to debugger srai x0, x0, 7 # 0x40705013 NOP encoding the semihosting call number 7If the -semihosting command-line argument is absent, then the new DSCR fields apply as normal. If the -semihosting command-line argument is present, and the ebreak is not surrounded by the required nops, then the new DSCR fields apply as normal. But if the command-line argument is present and the nops are present, then semihosting overrides the architecture and DSCR does not apply at all.
r~
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