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Re: [PATCH] riscv: Make semihosting configurable for all privilege modes
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH] riscv: Make semihosting configurable for all privilege modes |
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Date: |
Fri, 12 Aug 2022 19:31:59 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 |
On 8/12/22 17:50, Furquan Shaikh wrote:
Why do you need such fine-grained control? What is the use-case?
I ran into a problem when I was testing a project (with a microkernel
in M-mode and tasks in U-mode) that uses semihosting for debugging.
The semihosting worked fine for M-mode but not in U-mode.
Sure. This would be handled by Peter's proposed userspace-enable=on property.
As I started
digging into this, I realized that this is because qemu restricts
semihosting to only M and S modes. From reading the debug spec, I
understood that the DCSR presents options for ebreak behavior in each
mode including VS and VU.
I strongly suspect that VS also already works, since that's just
env->priv == PRV_S && riscv_cpu_virt_enabled(env)
VU would also be handled by userspace-enable=on.
I do not see any use for 5 separate properties.
r~
- Re: [PATCH] riscv: Make semihosting configurable for all privilege modes, (continued)
Re: [PATCH] riscv: Make semihosting configurable for all privilege modes, Peter Maydell, 2022/08/12
Re: [PATCH] riscv: Make semihosting configurable for all privilege modes, Richard Henderson, 2022/08/12