[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 38/66] accel/tcg: Drop addr member from SavedIOTLB
From: |
Richard Henderson |
Subject: |
[PATCH v2 38/66] accel/tcg: Drop addr member from SavedIOTLB |
Date: |
Mon, 22 Aug 2022 08:27:13 -0700 |
This field is only written, not read; remove it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 1 -
accel/tcg/cputlb.c | 7 +++----
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 500503da13..9e47184513 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -218,7 +218,6 @@ struct CPUWatchpoint {
* the memory regions get moved around by io_writex.
*/
typedef struct SavedIOTLB {
- hwaddr addr;
MemoryRegionSection *section;
hwaddr mr_offset;
} SavedIOTLB;
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index a37275bf8e..1509df96b4 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1386,12 +1386,11 @@ static uint64_t io_readx(CPUArchState *env,
CPUTLBEntryFull *full,
* This is read by tlb_plugin_lookup if the fulltlb entry doesn't match
* because of the side effect of io_writex changing memory layout.
*/
-static void save_iotlb_data(CPUState *cs, hwaddr addr,
- MemoryRegionSection *section, hwaddr mr_offset)
+static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section,
+ hwaddr mr_offset)
{
#ifdef CONFIG_PLUGIN
SavedIOTLB *saved = &cs->saved_iotlb;
- saved->addr = addr;
saved->section = section;
saved->mr_offset = mr_offset;
#endif
@@ -1420,7 +1419,7 @@ static void io_writex(CPUArchState *env, CPUTLBEntryFull
*full,
* The memory_region_dispatch may trigger a flush/resize
* so for plugins we save the iotlb_data just in case.
*/
- save_iotlb_data(cpu, full->xlat_section, section, mr_offset);
+ save_iotlb_data(cpu, section, mr_offset);
if (!qemu_mutex_iothread_locked()) {
qemu_mutex_lock_iothread();
--
2.34.1
- [PATCH v2 26/66] target/arm: Fold secure and non-secure a-profile mmu indexes, (continued)
- [PATCH v2 26/66] target/arm: Fold secure and non-secure a-profile mmu indexes, Richard Henderson, 2022/08/22
- [PATCH v2 29/66] target/arm: Introduce arm_hcr_el2_eff_secstate, Richard Henderson, 2022/08/22
- [PATCH v2 30/66] target/arm: Hoist read of *is_secure in S1_ptw_translate, Richard Henderson, 2022/08/22
- [PATCH v2 25/66] target/arm: Add is_secure parameter to do_ats_write, Richard Henderson, 2022/08/22
- [PATCH v2 31/66] target/arm: Fix S2 disabled check in S1_ptw_translate, Richard Henderson, 2022/08/22
- [PATCH v2 32/66] target/arm: Remove env argument from combined_attrs_fwb, Richard Henderson, 2022/08/22
- [PATCH v2 33/66] target/arm: Pass HCR to attribute subroutines., Richard Henderson, 2022/08/22
- [PATCH v2 34/66] target/arm: Fix ATS12NSO* from S PL1, Richard Henderson, 2022/08/22
- [PATCH v2 36/66] target/arm: Reorg get_phys_addr_disabled, Richard Henderson, 2022/08/22
- [PATCH v2 37/66] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull, Richard Henderson, 2022/08/22
- [PATCH v2 38/66] accel/tcg: Drop addr member from SavedIOTLB,
Richard Henderson <=
- [PATCH v2 39/66] accel/tcg: Suppress auto-invalidate in probe_access_internal, Richard Henderson, 2022/08/22
- [PATCH v2 35/66] target/arm: Split out get_phys_addr_disabled, Richard Henderson, 2022/08/22
- [PATCH v2 40/66] accel/tcg: Introduce probe_access_full, Richard Henderson, 2022/08/22
- [PATCH v2 41/66] accel/tcg: Introduce tlb_set_page_full, Richard Henderson, 2022/08/22
- [PATCH v2 48/66] target/arm: Add ARMMMUIdx_Phys_{S,NS}, Richard Henderson, 2022/08/22
- [PATCH v2 43/66] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA, Richard Henderson, 2022/08/22
- [PATCH v2 42/66] target/arm: Use tlb_set_page_full, Richard Henderson, 2022/08/22
- [PATCH v2 46/66] target/arm: Use probe_access_full for BTI, Richard Henderson, 2022/08/22
- [PATCH v2 50/66] target/arm: Use softmmu tlbs for page table walking, Richard Henderson, 2022/08/22
- [PATCH v2 44/66] target/arm: Enable TARGET_PAGE_ENTRY_EXTRA, Richard Henderson, 2022/08/22