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[PATCH v2 25/66] target/arm: Add is_secure parameter to do_ats_write
From: |
Richard Henderson |
Subject: |
[PATCH v2 25/66] target/arm: Add is_secure parameter to do_ats_write |
Date: |
Mon, 22 Aug 2022 08:27:00 -0700 |
Use get_phys_addr_with_secure directly. This is the one place
where the value of is_secure may not equal arm_is_secure(env).
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1fcfc85b76..09990ca096 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3105,7 +3105,8 @@ static CPAccessResult ats_access(CPUARMState *env, const
ARMCPRegInfo *ri,
#ifdef CONFIG_TCG
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
- MMUAccessType access_type, ARMMMUIdx mmu_idx)
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
+ bool is_secure)
{
bool ret;
uint64_t par64;
@@ -3113,7 +3114,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t
value,
ARMMMUFaultInfo fi = {};
GetPhysAddrResult res = {};
- ret = get_phys_addr(env, value, access_type, mmu_idx, &res, &fi);
+ ret = get_phys_addr_with_secure(env, value, access_type, mmu_idx,
+ is_secure, &res, &fi);
/*
* ATS operations only do S1 or S1+S2 translations, so we never
@@ -3285,6 +3287,7 @@ static void ats_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
switch (el) {
case 3:
mmu_idx = ARMMMUIdx_SE3;
+ secure = true;
break;
case 2:
g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
@@ -3306,6 +3309,7 @@ static void ats_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
switch (el) {
case 3:
mmu_idx = ARMMMUIdx_SE10_0;
+ secure = true;
break;
case 2:
g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
@@ -3321,16 +3325,18 @@ static void ats_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
case 4:
/* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
mmu_idx = ARMMMUIdx_E10_1;
+ secure = false;
break;
case 6:
/* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
mmu_idx = ARMMMUIdx_E10_0;
+ secure = false;
break;
default:
g_assert_not_reached();
}
- par64 = do_ats_write(env, value, access_type, mmu_idx);
+ par64 = do_ats_write(env, value, access_type, mmu_idx, secure);
A32_BANKED_CURRENT_REG_SET(env, par, par64);
#else
@@ -3346,7 +3352,8 @@ static void ats1h_write(CPUARMState *env, const
ARMCPRegInfo *ri,
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
uint64_t par64;
- par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
+ /* There is no SecureEL2 for AArch32. */
+ par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, false);
A32_BANKED_CURRENT_REG_SET(env, par, par64);
#else
@@ -3389,6 +3396,7 @@ static void ats_write64(CPUARMState *env, const
ARMCPRegInfo *ri,
break;
case 6: /* AT S1E3R, AT S1E3W */
mmu_idx = ARMMMUIdx_SE3;
+ secure = true;
break;
default:
g_assert_not_reached();
@@ -3407,7 +3415,8 @@ static void ats_write64(CPUARMState *env, const
ARMCPRegInfo *ri,
g_assert_not_reached();
}
- env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
+ env->cp15.par_el[1] = do_ats_write(env, value, access_type,
+ mmu_idx, secure);
#else
/* Handled by hardware accelerator. */
g_assert_not_reached();
--
2.34.1
- [PATCH v2 21/66] target/arm: Split out get_phys_addr_with_secure, (continued)
- [PATCH v2 21/66] target/arm: Split out get_phys_addr_with_secure, Richard Henderson, 2022/08/22
- [PATCH v2 22/66] target/arm: Add is_secure parameter to v7m_read_half_insn, Richard Henderson, 2022/08/22
- [PATCH v2 17/66] target/arm: Add is_secure parameter to get_phys_addr_lpae, Richard Henderson, 2022/08/22
- [PATCH v2 23/66] target/arm: Add TBFLAG_M32.SECURE, Richard Henderson, 2022/08/22
- [PATCH v2 24/66] target/arm: Merge regime_is_secure into get_phys_addr, Richard Henderson, 2022/08/22
- [PATCH v2 27/66] target/arm: Reorg regime_translation_disabled, Richard Henderson, 2022/08/22
- [PATCH v2 28/66] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M, Richard Henderson, 2022/08/22
- [PATCH v2 26/66] target/arm: Fold secure and non-secure a-profile mmu indexes, Richard Henderson, 2022/08/22
- [PATCH v2 29/66] target/arm: Introduce arm_hcr_el2_eff_secstate, Richard Henderson, 2022/08/22
- [PATCH v2 30/66] target/arm: Hoist read of *is_secure in S1_ptw_translate, Richard Henderson, 2022/08/22
- [PATCH v2 25/66] target/arm: Add is_secure parameter to do_ats_write,
Richard Henderson <=
- [PATCH v2 31/66] target/arm: Fix S2 disabled check in S1_ptw_translate, Richard Henderson, 2022/08/22
- [PATCH v2 32/66] target/arm: Remove env argument from combined_attrs_fwb, Richard Henderson, 2022/08/22
- [PATCH v2 33/66] target/arm: Pass HCR to attribute subroutines., Richard Henderson, 2022/08/22
- [PATCH v2 34/66] target/arm: Fix ATS12NSO* from S PL1, Richard Henderson, 2022/08/22
- [PATCH v2 36/66] target/arm: Reorg get_phys_addr_disabled, Richard Henderson, 2022/08/22
- [PATCH v2 37/66] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull, Richard Henderson, 2022/08/22
- [PATCH v2 38/66] accel/tcg: Drop addr member from SavedIOTLB, Richard Henderson, 2022/08/22
- [PATCH v2 39/66] accel/tcg: Suppress auto-invalidate in probe_access_internal, Richard Henderson, 2022/08/22
- [PATCH v2 35/66] target/arm: Split out get_phys_addr_disabled, Richard Henderson, 2022/08/22
- [PATCH v2 40/66] accel/tcg: Introduce probe_access_full, Richard Henderson, 2022/08/22