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[PATCH v2 24/66] target/arm: Merge regime_is_secure into get_phys_addr
From: |
Richard Henderson |
Subject: |
[PATCH v2 24/66] target/arm: Merge regime_is_secure into get_phys_addr |
Date: |
Mon, 22 Aug 2022 08:26:59 -0700 |
This is the last use of regime_is_secure; remove it
entirely before changing the layout of ARMMMUIdx.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/internals.h | 42 ----------------------------------------
target/arm/ptw.c | 44 ++++++++++++++++++++++++++++++++++++++++--
2 files changed, 42 insertions(+), 44 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 3ccc79f3d9..a231000965 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -670,48 +670,6 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
}
}
-/* Return true if this address translation regime is secure */
-static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
- switch (mmu_idx) {
- case ARMMMUIdx_E10_0:
- case ARMMMUIdx_E10_1:
- case ARMMMUIdx_E10_1_PAN:
- case ARMMMUIdx_E20_0:
- case ARMMMUIdx_E20_2:
- case ARMMMUIdx_E20_2_PAN:
- case ARMMMUIdx_Stage1_E0:
- case ARMMMUIdx_Stage1_E1:
- case ARMMMUIdx_Stage1_E1_PAN:
- case ARMMMUIdx_E2:
- case ARMMMUIdx_Stage2:
- case ARMMMUIdx_MPrivNegPri:
- case ARMMMUIdx_MUserNegPri:
- case ARMMMUIdx_MPriv:
- case ARMMMUIdx_MUser:
- return false;
- case ARMMMUIdx_SE3:
- case ARMMMUIdx_SE10_0:
- case ARMMMUIdx_SE10_1:
- case ARMMMUIdx_SE10_1_PAN:
- case ARMMMUIdx_SE20_0:
- case ARMMMUIdx_SE20_2:
- case ARMMMUIdx_SE20_2_PAN:
- case ARMMMUIdx_Stage1_SE0:
- case ARMMMUIdx_Stage1_SE1:
- case ARMMMUIdx_Stage1_SE1_PAN:
- case ARMMMUIdx_SE2:
- case ARMMMUIdx_Stage2_S:
- case ARMMMUIdx_MSPrivNegPri:
- case ARMMMUIdx_MSUserNegPri:
- case ARMMMUIdx_MSPriv:
- case ARMMMUIdx_MSUser:
- return true;
- default:
- g_assert_not_reached();
- }
-}
-
static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index c132d0cada..400ef00b63 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2518,9 +2518,49 @@ bool get_phys_addr(CPUARMState *env, target_ulong
address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
{
+ bool is_secure;
+
+ switch (mmu_idx) {
+ case ARMMMUIdx_E10_0:
+ case ARMMMUIdx_E10_1:
+ case ARMMMUIdx_E10_1_PAN:
+ case ARMMMUIdx_E20_0:
+ case ARMMMUIdx_E20_2:
+ case ARMMMUIdx_E20_2_PAN:
+ case ARMMMUIdx_Stage1_E0:
+ case ARMMMUIdx_Stage1_E1:
+ case ARMMMUIdx_Stage1_E1_PAN:
+ case ARMMMUIdx_E2:
+ case ARMMMUIdx_Stage2:
+ case ARMMMUIdx_MPrivNegPri:
+ case ARMMMUIdx_MUserNegPri:
+ case ARMMMUIdx_MPriv:
+ case ARMMMUIdx_MUser:
+ is_secure = false;
+ break;
+ case ARMMMUIdx_SE3:
+ case ARMMMUIdx_SE10_0:
+ case ARMMMUIdx_SE10_1:
+ case ARMMMUIdx_SE10_1_PAN:
+ case ARMMMUIdx_SE20_0:
+ case ARMMMUIdx_SE20_2:
+ case ARMMMUIdx_SE20_2_PAN:
+ case ARMMMUIdx_Stage1_SE0:
+ case ARMMMUIdx_Stage1_SE1:
+ case ARMMMUIdx_Stage1_SE1_PAN:
+ case ARMMMUIdx_SE2:
+ case ARMMMUIdx_Stage2_S:
+ case ARMMMUIdx_MSPrivNegPri:
+ case ARMMMUIdx_MSUserNegPri:
+ case ARMMMUIdx_MSPriv:
+ case ARMMMUIdx_MSUser:
+ is_secure = true;
+ break;
+ default:
+ g_assert_not_reached();
+ }
return get_phys_addr_with_secure(env, address, access_type, mmu_idx,
- regime_is_secure(env, mmu_idx),
- result, fi);
+ is_secure, result, fi);
}
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
--
2.34.1
- [PATCH v2 15/66] target/arm: Add secure parameter to get_phys_addr_pmsav8, (continued)
- [PATCH v2 15/66] target/arm: Add secure parameter to get_phys_addr_pmsav8, Richard Henderson, 2022/08/22
- [PATCH v2 14/66] target/arm: Add is_secure parameter to get_phys_addr_v6, Richard Henderson, 2022/08/22
- [PATCH v2 18/66] target/arm: Add secure parameter to get_phys_addr_pmsav7, Richard Henderson, 2022/08/22
- [PATCH v2 16/66] target/arm: Add is_secure parameter to pmsav7_use_background_region, Richard Henderson, 2022/08/22
- [PATCH v2 19/66] target/arm: Add is_secure parameter to regime_translation_disabled, Richard Henderson, 2022/08/22
- [PATCH v2 20/66] target/arm: Add is_secure parameter to get_phys_addr_pmsav5, Richard Henderson, 2022/08/22
- [PATCH v2 21/66] target/arm: Split out get_phys_addr_with_secure, Richard Henderson, 2022/08/22
- [PATCH v2 22/66] target/arm: Add is_secure parameter to v7m_read_half_insn, Richard Henderson, 2022/08/22
- [PATCH v2 17/66] target/arm: Add is_secure parameter to get_phys_addr_lpae, Richard Henderson, 2022/08/22
- [PATCH v2 23/66] target/arm: Add TBFLAG_M32.SECURE, Richard Henderson, 2022/08/22
- [PATCH v2 24/66] target/arm: Merge regime_is_secure into get_phys_addr,
Richard Henderson <=
- [PATCH v2 27/66] target/arm: Reorg regime_translation_disabled, Richard Henderson, 2022/08/22
- [PATCH v2 28/66] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M, Richard Henderson, 2022/08/22
- [PATCH v2 26/66] target/arm: Fold secure and non-secure a-profile mmu indexes, Richard Henderson, 2022/08/22
- [PATCH v2 29/66] target/arm: Introduce arm_hcr_el2_eff_secstate, Richard Henderson, 2022/08/22
- [PATCH v2 30/66] target/arm: Hoist read of *is_secure in S1_ptw_translate, Richard Henderson, 2022/08/22
- [PATCH v2 25/66] target/arm: Add is_secure parameter to do_ats_write, Richard Henderson, 2022/08/22
- [PATCH v2 31/66] target/arm: Fix S2 disabled check in S1_ptw_translate, Richard Henderson, 2022/08/22
- [PATCH v2 32/66] target/arm: Remove env argument from combined_attrs_fwb, Richard Henderson, 2022/08/22
- [PATCH v2 33/66] target/arm: Pass HCR to attribute subroutines., Richard Henderson, 2022/08/22
- [PATCH v2 34/66] target/arm: Fix ATS12NSO* from S PL1, Richard Henderson, 2022/08/22