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[PULL 19/60] ppc/pnv: add phb-id/chip-id PnvPHB4RootBus properties
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 19/60] ppc/pnv: add phb-id/chip-id PnvPHB4RootBus properties |
Date: |
Wed, 31 Aug 2022 15:49:53 -0300 |
The same rationale provided in the PHB3 bus case applies here.
Note: we could have merged both buses in a single object, like we did
with the root ports, and spare some boilerplate. The reason we opted to
preserve both buses objects is twofold:
- there's not user side advantage in doing so. Unifying the root ports
presents a clear user QOL change when we enable user created devices back.
The buses objects, aside from having a different QOM name, is transparent
to the user;
- we leave a door opened in case we want to increase the root port limit
for phb4/5 later on without having to deal with phb3 code.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220811163950.578927-3-danielhb413@gmail.com>
---
hw/pci-host/pnv_phb4.c | 51 ++++++++++++++++++++++++++++++++++
include/hw/pci-host/pnv_phb4.h | 10 +++++++
2 files changed, 61 insertions(+)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index b98c394713..824e1a73fb 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1551,6 +1551,12 @@ void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb)
pnv_phb4_set_irq, pnv_phb4_map_irq, phb,
&phb->pci_mmio, &phb->pci_io,
0, 4, TYPE_PNV_PHB4_ROOT_BUS);
+
+ object_property_set_int(OBJECT(pci->bus), "phb-id", phb->phb_id,
+ &error_abort);
+ object_property_set_int(OBJECT(pci->bus), "chip-id", phb->chip_id,
+ &error_abort);
+
pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb);
pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
}
@@ -1708,10 +1714,55 @@ static const TypeInfo pnv_phb5_type_info = {
.instance_size = sizeof(PnvPHB4),
};
+static void pnv_phb4_root_bus_get_prop(Object *obj, Visitor *v,
+ const char *name,
+ void *opaque, Error **errp)
+{
+ PnvPHB4RootBus *bus = PNV_PHB4_ROOT_BUS(obj);
+ uint64_t value = 0;
+
+ if (strcmp(name, "phb-id") == 0) {
+ value = bus->phb_id;
+ } else {
+ value = bus->chip_id;
+ }
+
+ visit_type_size(v, name, &value, errp);
+}
+
+static void pnv_phb4_root_bus_set_prop(Object *obj, Visitor *v,
+ const char *name,
+ void *opaque, Error **errp)
+
+{
+ PnvPHB4RootBus *bus = PNV_PHB4_ROOT_BUS(obj);
+ uint64_t value;
+
+ if (!visit_type_size(v, name, &value, errp)) {
+ return;
+ }
+
+ if (strcmp(name, "phb-id") == 0) {
+ bus->phb_id = value;
+ } else {
+ bus->chip_id = value;
+ }
+}
+
static void pnv_phb4_root_bus_class_init(ObjectClass *klass, void *data)
{
BusClass *k = BUS_CLASS(klass);
+ object_class_property_add(klass, "phb-id", "int",
+ pnv_phb4_root_bus_get_prop,
+ pnv_phb4_root_bus_set_prop,
+ NULL, NULL);
+
+ object_class_property_add(klass, "chip-id", "int",
+ pnv_phb4_root_bus_get_prop,
+ pnv_phb4_root_bus_set_prop,
+ NULL, NULL);
+
/*
* PHB4 has only a single root complex. Enforce the limit on the
* parent bus
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 20aa4819d3..50d4faa001 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -45,7 +45,17 @@ typedef struct PnvPhb4DMASpace {
QLIST_ENTRY(PnvPhb4DMASpace) list;
} PnvPhb4DMASpace;
+/*
+ * PHB4 PCIe Root Bus
+ */
#define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root"
+struct PnvPHB4RootBus {
+ PCIBus parent;
+
+ uint32_t chip_id;
+ uint32_t phb_id;
+};
+OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4RootBus, PNV_PHB4_ROOT_BUS)
/*
* PHB4 PCIe Host Bridge for PowerNV machines (POWER9)
--
2.37.2
- [PULL 11/60] ppc/pnv: add pnv-phb-root-port device, (continued)
- [PULL 11/60] ppc/pnv: add pnv-phb-root-port device, Daniel Henrique Barboza, 2022/08/31
- [PULL 12/60] ppc/pnv: remove pnv-phb3-root-port, Daniel Henrique Barboza, 2022/08/31
- [PULL 13/60] ppc/pnv: remove pnv-phb4-root-port, Daniel Henrique Barboza, 2022/08/31
- [PULL 15/60] ppc/pnv: remove pecc->rp_model, Daniel Henrique Barboza, 2022/08/31
- [PULL 14/60] ppc/pnv: remove root port name from pnv_phb_attach_root_port(), Daniel Henrique Barboza, 2022/08/31
- [PULL 16/60] ppc/pnv: remove PnvPHB4.version, Daniel Henrique Barboza, 2022/08/31
- [PULL 17/60] ppc/pnv: move attach_root_port helper to pnv-phb.c, Daniel Henrique Barboza, 2022/08/31
- [PULL 18/60] ppc/pnv: add phb-id/chip-id PnvPHB3RootBus properties, Daniel Henrique Barboza, 2022/08/31
- [PULL 20/60] ppc/pnv: set root port chassis and slot using Bus properties, Daniel Henrique Barboza, 2022/08/31
- [PULL 21/60] ppc/pnv: add helpers for pnv-phb user devices, Daniel Henrique Barboza, 2022/08/31
- [PULL 19/60] ppc/pnv: add phb-id/chip-id PnvPHB4RootBus properties,
Daniel Henrique Barboza <=
- [PULL 22/60] ppc/pnv: turn chip8->phbs[] into a PnvPHB* array, Daniel Henrique Barboza, 2022/08/31
- [PULL 24/60] ppc/pnv: add PHB4 helpers for user created pnv-phb, Daniel Henrique Barboza, 2022/08/31
- [PULL 23/60] ppc/pnv: enable user created pnv-phb for powernv8, Daniel Henrique Barboza, 2022/08/31
- [PULL 25/60] ppc/pnv: enable user created pnv-phb for powernv9, Daniel Henrique Barboza, 2022/08/31
- [PULL 26/60] ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs, Daniel Henrique Barboza, 2022/08/31
- [PULL 27/60] ppc/pnv: user creatable pnv-phb for powernv10, Daniel Henrique Barboza, 2022/08/31
- [PULL 29/60] ppc/pnv: fix QOM parenting of user creatable root ports, Daniel Henrique Barboza, 2022/08/31
- [PULL 28/60] ppc/pnv: consolidate pnv_parent_*_fixup() helpers, Daniel Henrique Barboza, 2022/08/31
- [PULL 30/60] ppc/ppc405: Remove taihu machine, Daniel Henrique Barboza, 2022/08/31
- [PULL 31/60] ppc/ppc405: Introduce a PPC405 generic machine, Daniel Henrique Barboza, 2022/08/31