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[PULL 34/60] ppc/ppc405: Introduce a PPC405 SoC
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 34/60] ppc/ppc405: Introduce a PPC405 SoC |
Date: |
Wed, 31 Aug 2022 15:50:08 -0300 |
From: Cédric Le Goater <clg@kaod.org>
It is an initial model to start QOMification of the PPC405 board.
QOM'ified devices will be reintroduced one by one. Start with the
memory regions, which name prefix is changed to "ppc405".
Also, initialize only one RAM bank. The second bank is a dummy one
(zero size) which is here to match the hard coded number of banks in
ppc405ep_init().
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20220809153904.485018-6-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc405.h | 16 ++++++++++++++++
hw/ppc/ppc405_boards.c | 23 ++++++++++++-----------
hw/ppc/ppc405_uc.c | 40 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 68 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 83f156f585..66dc21cdfe 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -25,6 +25,7 @@
#ifndef PPC405_H
#define PPC405_H
+#include "qom/object.h"
#include "hw/ppc/ppc4xx.h"
#define PPC405EP_SDRAM_BASE 0x00000000
@@ -62,6 +63,21 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+#define TYPE_PPC405_SOC "ppc405-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
+
+struct Ppc405SoCState {
+ /* Private */
+ DeviceState parent_obj;
+
+ /* Public */
+ MemoryRegion ram_banks[2];
+ hwaddr ram_bases[2], ram_sizes[2];
+
+ MemoryRegion *dram_mr;
+ hwaddr ram_size;
+};
+
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 381f39aa94..f029d6f415 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -57,6 +57,8 @@ struct Ppc405MachineState {
/* Private */
MachineState parent_obj;
/* Public */
+
+ Ppc405SoCState soc;
};
/*****************************************************************************/
@@ -232,11 +234,10 @@ static void boot_from_kernel(MachineState *machine,
PowerPCCPU *cpu)
static void ppc405_init(MachineState *machine)
{
+ Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
PowerPCCPU *cpu;
- MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
- hwaddr ram_bases[2], ram_sizes[2];
MemoryRegion *sysmem = get_system_memory();
DeviceState *uicdev;
@@ -247,16 +248,16 @@ static void ppc405_init(MachineState *machine)
exit(EXIT_FAILURE);
}
- /* XXX: fix this */
- memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias",
- machine->ram, 0, machine->ram_size);
- ram_bases[0] = 0;
- ram_sizes[0] = machine->ram_size;
- memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
- ram_bases[1] = 0x00000000;
- ram_sizes[1] = 0x00000000;
+ object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
+ TYPE_PPC405_SOC);
+ object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
+ machine->ram_size, &error_fatal);
+ object_property_set_link(OBJECT(&ppc405->soc), "dram",
+ OBJECT(machine->ram), &error_abort);
+ qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
- cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
+ cpu = ppc405ep_init(sysmem, ppc405->soc.ram_banks, ppc405->soc.ram_bases,
+ ppc405->soc.ram_sizes,
33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
/* allocate and load BIOS */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index d6420c88d3..adadb3a0ae 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -30,6 +30,7 @@
#include "hw/ppc/ppc.h"
#include "hw/i2c/ppc4xx_i2c.h"
#include "hw/irq.h"
+#include "hw/qdev-properties.h"
#include "ppc405.h"
#include "hw/char/serial.h"
#include "qemu/timer.h"
@@ -1530,3 +1531,42 @@ PowerPCCPU *ppc405ep_init(MemoryRegion
*address_space_mem,
return cpu;
}
+
+static void ppc405_soc_realize(DeviceState *dev, Error **errp)
+{
+ Ppc405SoCState *s = PPC405_SOC(dev);
+
+ /* Initialize only one bank */
+ s->ram_bases[0] = 0;
+ s->ram_sizes[0] = s->ram_size;
+ memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
+ "ppc405.sdram0", s->dram_mr,
+ s->ram_bases[0], s->ram_sizes[0]);
+}
+
+static Property ppc405_soc_properties[] = {
+ DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_soc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_soc_realize;
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc405_soc_properties);
+}
+
+static const TypeInfo ppc405_types[] = {
+ {
+ .name = TYPE_PPC405_SOC,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(Ppc405SoCState),
+ .class_init = ppc405_soc_class_init,
+ }
+};
+
+DEFINE_TYPES(ppc405_types)
--
2.37.2
- [PULL 23/60] ppc/pnv: enable user created pnv-phb for powernv8, (continued)
- [PULL 23/60] ppc/pnv: enable user created pnv-phb for powernv8, Daniel Henrique Barboza, 2022/08/31
- [PULL 25/60] ppc/pnv: enable user created pnv-phb for powernv9, Daniel Henrique Barboza, 2022/08/31
- [PULL 26/60] ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs, Daniel Henrique Barboza, 2022/08/31
- [PULL 27/60] ppc/pnv: user creatable pnv-phb for powernv10, Daniel Henrique Barboza, 2022/08/31
- [PULL 29/60] ppc/pnv: fix QOM parenting of user creatable root ports, Daniel Henrique Barboza, 2022/08/31
- [PULL 28/60] ppc/pnv: consolidate pnv_parent_*_fixup() helpers, Daniel Henrique Barboza, 2022/08/31
- [PULL 30/60] ppc/ppc405: Remove taihu machine, Daniel Henrique Barboza, 2022/08/31
- [PULL 31/60] ppc/ppc405: Introduce a PPC405 generic machine, Daniel Henrique Barboza, 2022/08/31
- [PULL 32/60] ppc/ppc405: Move devices under the ref405ep machine, Daniel Henrique Barboza, 2022/08/31
- [PULL 33/60] ppc/ppc405: Move SRAM under the ref405ep machine, Daniel Henrique Barboza, 2022/08/31
- [PULL 34/60] ppc/ppc405: Introduce a PPC405 SoC,
Daniel Henrique Barboza <=
- [PULL 35/60] ppc/ppc405: Start QOMification of the SoC, Daniel Henrique Barboza, 2022/08/31
- [PULL 37/60] ppc/ppc4xx: Introduce a DCR device model, Daniel Henrique Barboza, 2022/08/31
- [PULL 36/60] ppc/ppc405: QOM'ify CPU, Daniel Henrique Barboza, 2022/08/31
- [PULL 38/60] ppc/ppc405: QOM'ify CPC, Daniel Henrique Barboza, 2022/08/31
- [PULL 39/60] ppc/ppc405: QOM'ify GPT, Daniel Henrique Barboza, 2022/08/31
- [PULL 40/60] ppc/ppc405: QOM'ify OCM, Daniel Henrique Barboza, 2022/08/31
- [PULL 41/60] ppc/ppc405: QOM'ify GPIO, Daniel Henrique Barboza, 2022/08/31
- [PULL 42/60] ppc/ppc405: QOM'ify DMA, Daniel Henrique Barboza, 2022/08/31
- [PULL 43/60] ppc/ppc405: QOM'ify EBC, Daniel Henrique Barboza, 2022/08/31
- [PULL 44/60] ppc/ppc405: QOM'ify OPBA, Daniel Henrique Barboza, 2022/08/31