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[PULL 37/60] ppc/ppc4xx: Introduce a DCR device model
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 37/60] ppc/ppc4xx: Introduce a DCR device model |
Date: |
Wed, 31 Aug 2022 15:50:11 -0300 |
From: Cédric Le Goater <clg@kaod.org>
The Device Control Registers (DCR) of on-SoC devices are accessed by
software through the use of the mtdcr and mfdcr instructions. These
are converted in transactions on a side band bus, the DCR bus, which
connects the on-SoC devices to the CPU.
Ideally, we should model these accesses with a DCR namespace and DCR
memory regions but today the DCR handlers are installed in a DCR table
under the CPU. Instead, introduce a little device model wrapper to hold
a CPU link and handle registration of DCR handlers.
The DCR device inherits from SysBus because most of these devices also
have MMIO regions and/or IRQs. Being a SysBusDevice makes things easier
to install the device model in the overall SoC.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: Explicit opaque parameter for dcr callbacks]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<9b21bdf55e0a728f093bad299e030d98f302ded0.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc4xx_devs.c | 41 +++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/ppc4xx.h | 17 +++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 069b511951..f4d7ae9567 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -664,3 +664,44 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum,
uint8_t rxcnum,
mal, &dcr_read_mal, &dcr_write_mal);
}
}
+
+/* PPC4xx_DCR_DEVICE */
+
+void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
+ dcr_read_cb dcr_read, dcr_write_cb dcr_write)
+{
+ assert(dev->cpu);
+ ppc_dcr_register(&dev->cpu->env, dcrn, opaque, dcr_read, dcr_write);
+}
+
+bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
+ Error **errp)
+{
+ object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
+ return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
+}
+
+static Property ppc4xx_dcr_properties[] = {
+ DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU,
+ PowerPCCPU *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ device_class_set_props(dc, ppc4xx_dcr_properties);
+}
+
+static const TypeInfo ppc4xx_types[] = {
+ {
+ .name = TYPE_PPC4xx_DCR_DEVICE,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc4xxDcrDeviceState),
+ .class_init = ppc4xx_dcr_class_init,
+ .abstract = true,
+ }
+};
+
+DEFINE_TYPES(ppc4xx_types)
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 591e2421a3..a537a5567b 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -27,6 +27,7 @@
#include "hw/ppc/ppc.h"
#include "exec/memory.h"
+#include "hw/sysbus.h"
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
MemoryRegion ram_memories[],
@@ -44,4 +45,20 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum,
uint8_t rxcnum,
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
+/*
+ * Generic DCR device
+ */
+#define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
+struct Ppc4xxDcrDeviceState {
+ SysBusDevice parent_obj;
+
+ PowerPCCPU *cpu;
+};
+
+void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
+ dcr_read_cb dcr_read, dcr_write_cb dcr_write);
+bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
+ Error **errp);
+
#endif /* PPC4XX_H */
--
2.37.2
- [PULL 26/60] ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs, (continued)
- [PULL 26/60] ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs, Daniel Henrique Barboza, 2022/08/31
- [PULL 27/60] ppc/pnv: user creatable pnv-phb for powernv10, Daniel Henrique Barboza, 2022/08/31
- [PULL 29/60] ppc/pnv: fix QOM parenting of user creatable root ports, Daniel Henrique Barboza, 2022/08/31
- [PULL 28/60] ppc/pnv: consolidate pnv_parent_*_fixup() helpers, Daniel Henrique Barboza, 2022/08/31
- [PULL 30/60] ppc/ppc405: Remove taihu machine, Daniel Henrique Barboza, 2022/08/31
- [PULL 31/60] ppc/ppc405: Introduce a PPC405 generic machine, Daniel Henrique Barboza, 2022/08/31
- [PULL 32/60] ppc/ppc405: Move devices under the ref405ep machine, Daniel Henrique Barboza, 2022/08/31
- [PULL 33/60] ppc/ppc405: Move SRAM under the ref405ep machine, Daniel Henrique Barboza, 2022/08/31
- [PULL 34/60] ppc/ppc405: Introduce a PPC405 SoC, Daniel Henrique Barboza, 2022/08/31
- [PULL 35/60] ppc/ppc405: Start QOMification of the SoC, Daniel Henrique Barboza, 2022/08/31
- [PULL 37/60] ppc/ppc4xx: Introduce a DCR device model,
Daniel Henrique Barboza <=
- [PULL 36/60] ppc/ppc405: QOM'ify CPU, Daniel Henrique Barboza, 2022/08/31
- [PULL 38/60] ppc/ppc405: QOM'ify CPC, Daniel Henrique Barboza, 2022/08/31
- [PULL 39/60] ppc/ppc405: QOM'ify GPT, Daniel Henrique Barboza, 2022/08/31
- [PULL 40/60] ppc/ppc405: QOM'ify OCM, Daniel Henrique Barboza, 2022/08/31
- [PULL 41/60] ppc/ppc405: QOM'ify GPIO, Daniel Henrique Barboza, 2022/08/31
- [PULL 42/60] ppc/ppc405: QOM'ify DMA, Daniel Henrique Barboza, 2022/08/31
- [PULL 43/60] ppc/ppc405: QOM'ify EBC, Daniel Henrique Barboza, 2022/08/31
- [PULL 44/60] ppc/ppc405: QOM'ify OPBA, Daniel Henrique Barboza, 2022/08/31
- [PULL 45/60] ppc/ppc405: QOM'ify POB, Daniel Henrique Barboza, 2022/08/31
- [PULL 46/60] ppc/ppc405: QOM'ify PLB, Daniel Henrique Barboza, 2022/08/31