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[PULL 45/60] ppc/ppc405: QOM'ify POB
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 45/60] ppc/ppc405: QOM'ify POB |
Date: |
Wed, 31 Aug 2022 15:50:19 -0300 |
From: Cédric Le Goater <clg@kaod.org>
POB is currently modeled as a simple DCR device.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<2bb1a89182523059ecb0e8d20c22a293534dec17.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc405.h | 12 ++++++++++
hw/ppc/ppc405_uc.c | 56 ++++++++++++++++++++++++++--------------------
2 files changed, 44 insertions(+), 24 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index d63c2acdc7..4140e811d5 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* PLB to OPB bridge */
+#define TYPE_PPC405_POB "ppc405-pob"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
+struct Ppc405PobState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ uint32_t bear;
+ uint32_t besr0;
+ uint32_t besr1;
+};
+
/* OPB arbitrer */
#define TYPE_PPC405_OPBA "ppc405-opba"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
@@ -220,6 +231,7 @@ struct Ppc405SoCState {
Ppc405DmaState dma;
Ppc405EbcState ebc;
Ppc405OpbaState opba;
+ Ppc405PobState pob;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 2c482bc25c..e5604c3421 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -234,19 +234,11 @@ enum {
POB0_BEAR = 0x0A4,
};
-typedef struct ppc4xx_pob_t ppc4xx_pob_t;
-struct ppc4xx_pob_t {
- uint32_t bear;
- uint32_t besr0;
- uint32_t besr1;
-};
-
-static uint32_t dcr_read_pob (void *opaque, int dcrn)
+static uint32_t dcr_read_pob(void *opaque, int dcrn)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = opaque;
uint32_t ret;
- pob = opaque;
switch (dcrn) {
case POB0_BEAR:
ret = pob->bear;
@@ -266,11 +258,10 @@ static uint32_t dcr_read_pob (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_pob(void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = opaque;
- pob = opaque;
switch (dcrn) {
case POB0_BEAR:
/* Read only */
@@ -286,26 +277,34 @@ static void dcr_write_pob (void *opaque, int dcrn,
uint32_t val)
}
}
-static void ppc4xx_pob_reset (void *opaque)
+static void ppc405_pob_reset(DeviceState *dev)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = PPC405_POB(dev);
- pob = opaque;
/* No error */
pob->bear = 0x00000000;
pob->besr0 = 0x0000000;
pob->besr1 = 0x0000000;
}
-static void ppc4xx_pob_init(CPUPPCState *env)
+static void ppc405_pob_realize(DeviceState *dev, Error **errp)
+{
+ Ppc405PobState *pob = PPC405_POB(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ ppc4xx_dcr_register(dcr, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
+ ppc4xx_dcr_register(dcr, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
+ ppc4xx_dcr_register(dcr, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
+}
+
+static void ppc405_pob_class_init(ObjectClass *oc, void *data)
{
- ppc4xx_pob_t *pob;
+ DeviceClass *dc = DEVICE_CLASS(oc);
- pob = g_new0(ppc4xx_pob_t, 1);
- ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
- ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
- ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
- qemu_register_reset(ppc4xx_pob_reset, pob);
+ dc->realize = ppc405_pob_realize;
+ dc->reset = ppc405_pob_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1373,6 +1372,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
+
+ object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
}
static void ppc405_reset(void *opaque)
@@ -1407,7 +1408,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
ppc4xx_plb_init(env);
/* PLB to OPB bridge */
- ppc4xx_pob_init(env);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) {
+ return;
+ }
/* OBP arbitrer */
sbd = SYS_BUS_DEVICE(&s->opba);
@@ -1527,6 +1530,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void
*data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_POB,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405PobState),
+ .class_init = ppc405_pob_class_init,
+ }, {
.name = TYPE_PPC405_OPBA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405OpbaState),
--
2.37.2
- [PULL 35/60] ppc/ppc405: Start QOMification of the SoC, (continued)
- [PULL 35/60] ppc/ppc405: Start QOMification of the SoC, Daniel Henrique Barboza, 2022/08/31
- [PULL 37/60] ppc/ppc4xx: Introduce a DCR device model, Daniel Henrique Barboza, 2022/08/31
- [PULL 36/60] ppc/ppc405: QOM'ify CPU, Daniel Henrique Barboza, 2022/08/31
- [PULL 38/60] ppc/ppc405: QOM'ify CPC, Daniel Henrique Barboza, 2022/08/31
- [PULL 39/60] ppc/ppc405: QOM'ify GPT, Daniel Henrique Barboza, 2022/08/31
- [PULL 40/60] ppc/ppc405: QOM'ify OCM, Daniel Henrique Barboza, 2022/08/31
- [PULL 41/60] ppc/ppc405: QOM'ify GPIO, Daniel Henrique Barboza, 2022/08/31
- [PULL 42/60] ppc/ppc405: QOM'ify DMA, Daniel Henrique Barboza, 2022/08/31
- [PULL 43/60] ppc/ppc405: QOM'ify EBC, Daniel Henrique Barboza, 2022/08/31
- [PULL 44/60] ppc/ppc405: QOM'ify OPBA, Daniel Henrique Barboza, 2022/08/31
- [PULL 45/60] ppc/ppc405: QOM'ify POB,
Daniel Henrique Barboza <=
- [PULL 46/60] ppc/ppc405: QOM'ify PLB, Daniel Henrique Barboza, 2022/08/31
- [PULL 47/60] ppc/ppc405: QOM'ify MAL, Daniel Henrique Barboza, 2022/08/31
- [PULL 49/60] ppc4xx: Rename ppc405-plb to ppc4xx-plb, Daniel Henrique Barboza, 2022/08/31
- [PULL 48/60] ppc4xx: Move PLB model to ppc4xx_devs.c, Daniel Henrique Barboza, 2022/08/31
- [PULL 50/60] ppc4xx: Move EBC model to ppc4xx_devs.c, Daniel Henrique Barboza, 2022/08/31
- [PULL 51/60] ppc4xx: Rename ppc405-ebc to ppc4xx-ebc, Daniel Henrique Barboza, 2022/08/31
- [PULL 52/60] ppc/ppc405: Use an embedded PPCUIC model in SoC state, Daniel Henrique Barboza, 2022/08/31
- [PULL 53/60] hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device, Daniel Henrique Barboza, 2022/08/31
- [PULL 54/60] ppc/ppc405: Use an explicit I2C object, Daniel Henrique Barboza, 2022/08/31
- [PULL 55/60] ppc/ppc405: QOM'ify FPGA, Daniel Henrique Barboza, 2022/08/31