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[PATCH v2 4/5] tcg: Add host memory barriers to cpu_ldst.h interfaces
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From: |
Richard Henderson |
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Subject: |
[PATCH v2 4/5] tcg: Add host memory barriers to cpu_ldst.h interfaces |
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Date: |
Sun, 5 Mar 2023 17:57:09 -0800 |
Bring the majority of helpers into line with the rest of
tcg in respecting guest memory ordering.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 14 ++++++++++++++
accel/tcg/cputlb.c | 2 ++
accel/tcg/user-exec.c | 14 ++++++++++++++
3 files changed, 30 insertions(+)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index b76b597878..0edda5f89f 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -1191,6 +1191,20 @@ static inline size_t tcg_current_code_size(TCGContext *s)
# define tcg_req_mo(type) ((type) & ~TCG_TARGET_DEFAULT_MO)
#endif
+/**
+ * tcg_req_mo:
+ * @type: TCGBar
+ *
+ * If tcg_req_mo indicates a barrier for @type is required for the
+ * guest memory model, issue a host memory barrier.
+ */
+#define cpu_req_mo(type) \
+ do { \
+ if (tcg_req_mo(type)) { \
+ smp_mb(); \
+ } \
+ } while (0)
+
/**
* tcg_qemu_tb_exec:
* @env: pointer to CPUArchState for the CPU
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index e984a98dc4..6a04514427 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2174,6 +2174,7 @@ static inline uint64_t cpu_load_helper(CPUArchState *env,
abi_ptr addr,
{
uint64_t ret;
+ cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
ret = full_load(env, addr, oi, retaddr);
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
return ret;
@@ -2586,6 +2587,7 @@ static inline void cpu_store_helper(CPUArchState *env,
target_ulong addr,
uint64_t val, MemOpIdx oi, uintptr_t ra,
FullStoreHelper *full_store)
{
+ cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
full_store(env, addr, val, oi, ra);
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
}
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 7b37fd229e..489459ae17 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -942,6 +942,7 @@ uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr,
validate_memop(oi, MO_UB);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
ret = ldub_p(haddr);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
@@ -956,6 +957,7 @@ uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr,
validate_memop(oi, MO_BEUW);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
ret = lduw_be_p(haddr);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
@@ -970,6 +972,7 @@ uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr,
validate_memop(oi, MO_BEUL);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
ret = ldl_be_p(haddr);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
@@ -984,6 +987,7 @@ uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr,
validate_memop(oi, MO_BEUQ);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
ret = ldq_be_p(haddr);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
@@ -998,6 +1002,7 @@ uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr,
validate_memop(oi, MO_LEUW);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
ret = lduw_le_p(haddr);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
@@ -1012,6 +1017,7 @@ uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr,
validate_memop(oi, MO_LEUL);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
ret = ldl_le_p(haddr);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
@@ -1026,6 +1032,7 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr,
validate_memop(oi, MO_LEUQ);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
ret = ldq_le_p(haddr);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
@@ -1075,6 +1082,7 @@ void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t
val,
validate_memop(oi, MO_UB);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
stb_p(haddr, val);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
@@ -1087,6 +1095,7 @@ void cpu_stw_be_mmu(CPUArchState *env, abi_ptr addr,
uint16_t val,
validate_memop(oi, MO_BEUW);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
stw_be_p(haddr, val);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
@@ -1099,6 +1108,7 @@ void cpu_stl_be_mmu(CPUArchState *env, abi_ptr addr,
uint32_t val,
validate_memop(oi, MO_BEUL);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
stl_be_p(haddr, val);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
@@ -1111,6 +1121,7 @@ void cpu_stq_be_mmu(CPUArchState *env, abi_ptr addr,
uint64_t val,
validate_memop(oi, MO_BEUQ);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
stq_be_p(haddr, val);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
@@ -1123,6 +1134,7 @@ void cpu_stw_le_mmu(CPUArchState *env, abi_ptr addr,
uint16_t val,
validate_memop(oi, MO_LEUW);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
stw_le_p(haddr, val);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
@@ -1135,6 +1147,7 @@ void cpu_stl_le_mmu(CPUArchState *env, abi_ptr addr,
uint32_t val,
validate_memop(oi, MO_LEUL);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
stl_le_p(haddr, val);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
@@ -1147,6 +1160,7 @@ void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr,
uint64_t val,
validate_memop(oi, MO_LEUQ);
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
stq_le_p(haddr, val);
clear_helper_retaddr();
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
--
2.34.1