qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [PULL 11/29] target/riscv: Convert RV32F insns to decod


From: Philippe Mathieu-Daudé
Subject: Re: [Qemu-devel] [PULL 11/29] target/riscv: Convert RV32F insns to decodetree
Date: Mon, 6 Mar 2023 15:11:23 +0100
User-agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.8.0

Hi Palmer, Bastian,

(old patch)

On 12/3/19 14:15, Palmer Dabbelt wrote:
From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
  target/riscv/insn32.decode              |  35 +++
  target/riscv/insn_trans/trans_rvf.inc.c | 379 ++++++++++++++++++++++++
  target/riscv/translate.c                |   1 +
  3 files changed, 415 insertions(+)
  create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c


+static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
+{
+    /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
+    REQUIRE_FPU;
+    REQUIRE_EXT(ctx, RVF);
+
+    TCGv t0 = tcg_temp_new();
+
+#if defined(TARGET_RISCV64)

Just noticed this while reviewing Richard's "tcg: Remove tcg_const_*'
recent series, shouldn't be this #if condition inverted?

+    tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
+#else
+    tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
+#endif
+
+    gen_set_gpr(a->rd, t0);
+    tcg_temp_free(t0);
+
+    return true;
+}




reply via email to

[Prev in Thread] Current Thread [Next in Thread]