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[PULL 05/21] target/arm: Simplify register counting in arm_gen_dynamic_s
From: |
Peter Maydell |
Subject: |
[PULL 05/21] target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml |
Date: |
Mon, 6 Mar 2023 15:34:19 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
Rather than increment base_reg and num, compute num from the change
to base_reg at the end. Clean up some nearby comments.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/gdbstub64.c | 27 ++++++++++++++++-----------
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 811833d8dec..070ba20d991 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -277,32 +277,35 @@ static void output_vector_union_type(GString *s, int
reg_width)
g_string_append(s, "</union>");
}
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
{
ARMCPU *cpu = ARM_CPU(cs);
GString *s = g_string_new(NULL);
DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
- int i, reg_width = (cpu->sve_max_vq * 128);
- info->num = 0;
+ int reg_width = cpu->sve_max_vq * 128;
+ int base_reg = orig_base_reg;
+ int i;
+
g_string_printf(s, "<?xml version=\"1.0\"?>");
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
+ /* Create the vector union type. */
output_vector_union_type(s, reg_width);
- /* Finally the sve prefix type */
+ /* Create the predicate vector type. */
g_string_append_printf(s,
"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
reg_width / 8);
- /* Then define each register in parts for each vq */
+ /* Define the vector registers. */
for (i = 0; i < 32; i++) {
g_string_append_printf(s,
"<reg name=\"z%d\" bitsize=\"%d\""
" regnum=\"%d\" type=\"svev\"/>",
i, reg_width, base_reg++);
- info->num++;
}
+
/* fpscr & status registers */
g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
" regnum=\"%d\" group=\"float\""
@@ -310,27 +313,29 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
" regnum=\"%d\" group=\"float\""
" type=\"int\"/>", base_reg++);
- info->num += 2;
+ /* Define the predicate registers. */
for (i = 0; i < 16; i++) {
g_string_append_printf(s,
"<reg name=\"p%d\" bitsize=\"%d\""
" regnum=\"%d\" type=\"svep\"/>",
i, cpu->sve_max_vq * 16, base_reg++);
- info->num++;
}
g_string_append_printf(s,
"<reg name=\"ffr\" bitsize=\"%d\""
" regnum=\"%d\" group=\"vector\""
" type=\"svep\"/>",
cpu->sve_max_vq * 16, base_reg++);
+
+ /* Define the vector length pseudo-register. */
g_string_append_printf(s,
"<reg name=\"vg\" bitsize=\"64\""
" regnum=\"%d\" type=\"int\"/>",
base_reg++);
- info->num += 2;
- g_string_append_printf(s, "</feature>");
- info->desc = g_string_free(s, false);
+ g_string_append_printf(s, "</feature>");
+
+ info->desc = g_string_free(s, false);
+ info->num = base_reg - orig_base_reg;
return info->num;
}
--
2.34.1
- [PULL 00/21] target-arm queue, Peter Maydell, 2023/03/06
- [PULL 01/21] target/arm: Normalize aarch64 gdbstub get/set function names, Peter Maydell, 2023/03/06
- [PULL 05/21] target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml,
Peter Maydell <=
- [PULL 02/21] target/arm: Unexport arm_gen_dynamic_sysreg_xml, Peter Maydell, 2023/03/06
- [PULL 09/21] target/arm: Simplify iteration over bit widths, Peter Maydell, 2023/03/06
- [PULL 04/21] target/arm: Split out output_vector_union_type, Peter Maydell, 2023/03/06
- [PULL 03/21] target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c, Peter Maydell, 2023/03/06
- [PULL 07/21] target/arm: Fix svep width in arm_gen_dynamic_svereg_xml, Peter Maydell, 2023/03/06
- [PULL 08/21] target/arm: Add name argument to output_vector_union_type, Peter Maydell, 2023/03/06
- [PULL 10/21] target/arm: Create pauth_ptr_mask, Peter Maydell, 2023/03/06
- [PULL 06/21] target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml, Peter Maydell, 2023/03/06
- [PULL 12/21] target/arm: Export arm_v7m_mrs_control, Peter Maydell, 2023/03/06
- [PULL 15/21] target/arm: Handle m-profile in arm_is_secure, Peter Maydell, 2023/03/06