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[PATCH 33/45] target/riscv: Add zvksh cpu property
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From: |
Lawrence Hunter |
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Subject: |
[PATCH 33/45] target/riscv: Add zvksh cpu property |
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Date: |
Fri, 10 Mar 2023 09:12:03 +0000 |
From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
---
target/riscv/cpu.c | 4 +++-
target/riscv/cpu.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b3f9638067..e218a00a2d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -113,6 +113,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zvkned, true, PRIV_VERSION_1_12_0, ext_zvkned),
ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha),
ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb),
+ ISA_EXT_DATA_ENTRY(zvksh, true, PRIV_VERSION_1_12_0, ext_zvksh),
ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
@@ -1219,7 +1220,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
* In principle zve*x would also suffice here, were they supported
* in qemu
*/
- if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) &&
+ if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha ||
+ cpu->cfg.ext_zvksh) &&
!(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f ||
cpu->cfg.ext_zve64d || cpu->cfg.ext_v)) {
error_setg(
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5d101fc405..3b0f322f3e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -474,6 +474,7 @@ struct RISCVCPUConfig {
bool ext_zvkned;
bool ext_zvknha;
bool ext_zvknhb;
+ bool ext_zvksh;
bool ext_zmmul;
bool ext_zvfh;
bool ext_zvfhmin;
--
2.39.2
- [PATCH 34/45] target/riscv: Add vsm3me.vv decoding, translation and execution support, (continued)
- [PATCH 34/45] target/riscv: Add vsm3me.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 37/45] target/riscv: Add zvkg cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 40/45] target/riscv: Expose zvkg cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 45/45] target/riscv: Expose Zvksed property, Lawrence Hunter, 2023/03/10
- [PATCH 36/45] target/riscv: Expose zvksh cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 44/45] target/riscv: Add Zvksed support, Lawrence Hunter, 2023/03/10
- [PATCH 41/45] crypto: Create sm4_subword, Lawrence Hunter, 2023/03/10
- [PATCH 39/45] target/riscv: Add vghsh.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 42/45] crypto: Add SM4 constant parameter CK, Lawrence Hunter, 2023/03/10
- [PATCH 38/45] target/riscv: Add vgmul.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 33/45] target/riscv: Add zvksh cpu property,
Lawrence Hunter <=
- [PATCH 30/45] target/riscv: Add vsha2ms.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- Re: [PATCH 00/45] Add RISC-V vector cryptographic instruction set support, Christoph Müllner, 2023/03/21
- [PATCH 00/45] Add RISC-V vector cryptographic instruction set support, Lawrence Hunter, 2023/03/10
- [PATCH 05/45] target/riscv: Add vclmul.vx decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 07/45] target/riscv: Add vclmulh.vx decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 09/45] qemu/bitops.h: Limit rotate amounts, Lawrence Hunter, 2023/03/10
- [PATCH 03/45] target/riscv: Add vclmul.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 01/45] target/riscv: Add zvkb cpu property, Lawrence Hunter, 2023/03/10