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[PATCH 29/45] target/riscv: Add zvknh cpu properties
From: |
Lawrence Hunter |
Subject: |
[PATCH 29/45] target/riscv: Add zvknh cpu properties |
Date: |
Fri, 10 Mar 2023 16:03:30 +0000 |
From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
---
target/riscv/cpu.c | 11 ++++++++++-
target/riscv/cpu.h | 2 ++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cd87eec919..3ffbdd53cc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -111,6 +111,8 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb),
ISA_EXT_DATA_ENTRY(zvkned, true, PRIV_VERSION_1_12_0, ext_zvkned),
+ ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha),
+ ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb),
ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
@@ -1217,7 +1219,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
* In principle zve*x would also suffice here, were they supported
* in qemu
*/
- if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkned) &&
+ if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) &&
!(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f ||
cpu->cfg.ext_zve64d || cpu->cfg.ext_v)) {
error_setg(
@@ -1225,6 +1227,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+ if (cpu->cfg.ext_zvknhb &&
+ !(cpu->cfg.ext_zve64f || cpu->cfg.ext_zve64d || cpu->cfg.ext_v)) {
+ error_setg(errp,
+ "Zvknhb extension requires V or Zve64{f,d} extensions");
+ return;
+ }
+
#ifndef CONFIG_USER_ONLY
if (cpu->cfg.pmu_num) {
if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4f3b97e0f1..5d101fc405 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -472,6 +472,8 @@ struct RISCVCPUConfig {
bool ext_zve64d;
bool ext_zvkb;
bool ext_zvkned;
+ bool ext_zvknha;
+ bool ext_zvknhb;
bool ext_zmmul;
bool ext_zvfh;
bool ext_zvfhmin;
--
2.39.2
- [PATCH 17/45] target/riscv: Add vaesef.vv decoding, translation and execution support, (continued)
- [PATCH 17/45] target/riscv: Add vaesef.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 21/45] target/riscv: Add vaesdm.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 23/45] target/riscv: Add vaesz.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 25/45] target/riscv: Add vaesem.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 24/45] target/riscv: Add vaesem.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 26/45] target/riscv: Add vaeskf1.vi decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 27/45] target/riscv: Add vaeskf2.vi decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 28/45] target/riscv: Expose zvkned cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 13/45] target/riscv: Add vrev8.v decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 20/45] target/riscv: Add vaesdf.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 29/45] target/riscv: Add zvknh cpu properties,
Lawrence Hunter <=
- [PATCH 10/45] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 04/45] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/03/10
- [PATCH 35/45] target/riscv: Add vsm3c.vi decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 45/45] target/riscv: Expose Zvksed property, Lawrence Hunter, 2023/03/10
- [PATCH 32/45] target/riscv: Expose zvknh cpu properties, Lawrence Hunter, 2023/03/10
- [PATCH 37/45] target/riscv: Add zvkg cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 30/45] target/riscv: Add vsha2ms.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 31/45] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 42/45] crypto: Add SM4 constant parameter CK, Lawrence Hunter, 2023/03/10
- [PATCH 33/45] target/riscv: Add zvksh cpu property, Lawrence Hunter, 2023/03/10
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