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[PATCH 37/45] target/riscv: Add zvkg cpu property
From: |
Lawrence Hunter |
Subject: |
[PATCH 37/45] target/riscv: Add zvkg cpu property |
Date: |
Fri, 10 Mar 2023 16:03:38 +0000 |
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
---
target/riscv/cpu.c | 5 +++--
target/riscv/cpu.h | 1 +
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c136a17112..79079d517d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb),
+ ISA_EXT_DATA_ENTRY(zvkg, true, PRIV_VERSION_1_12_0, ext_zvkg),
ISA_EXT_DATA_ENTRY(zvkned, true, PRIV_VERSION_1_12_0, ext_zvkned),
ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha),
ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb),
@@ -1220,8 +1221,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
* In principle zve*x would also suffice here, were they supported
* in qemu
*/
- if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha ||
- cpu->cfg.ext_zvksh) &&
+ if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
+ cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) &&
!(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f ||
cpu->cfg.ext_zve64d || cpu->cfg.ext_v)) {
error_setg(
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3b0f322f3e..40c4e23209 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -471,6 +471,7 @@ struct RISCVCPUConfig {
bool ext_zve64f;
bool ext_zve64d;
bool ext_zvkb;
+ bool ext_zvkg;
bool ext_zvkned;
bool ext_zvknha;
bool ext_zvknhb;
--
2.39.2
- [PATCH 27/45] target/riscv: Add vaeskf2.vi decoding, translation and execution support, (continued)
- [PATCH 27/45] target/riscv: Add vaeskf2.vi decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 28/45] target/riscv: Expose zvkned cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 13/45] target/riscv: Add vrev8.v decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 20/45] target/riscv: Add vaesdf.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 29/45] target/riscv: Add zvknh cpu properties, Lawrence Hunter, 2023/03/10
- [PATCH 10/45] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 04/45] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/03/10
- [PATCH 35/45] target/riscv: Add vsm3c.vi decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 45/45] target/riscv: Expose Zvksed property, Lawrence Hunter, 2023/03/10
- [PATCH 32/45] target/riscv: Expose zvknh cpu properties, Lawrence Hunter, 2023/03/10
- [PATCH 37/45] target/riscv: Add zvkg cpu property,
Lawrence Hunter <=
- [PATCH 30/45] target/riscv: Add vsha2ms.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 31/45] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 42/45] crypto: Add SM4 constant parameter CK, Lawrence Hunter, 2023/03/10
- [PATCH 33/45] target/riscv: Add zvksh cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 44/45] target/riscv: Add Zvksed support, Lawrence Hunter, 2023/03/10
- [PATCH 38/45] target/riscv: Add vgmul.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 36/45] target/riscv: Expose zvksh cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 43/45] target/riscv: Add zvksed cfg property, Lawrence Hunter, 2023/03/10
- [PATCH 40/45] target/riscv: Expose zvkg cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 34/45] target/riscv: Add vsm3me.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10