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[PULL 03/24] target/s390x: Implement Early Exception Recognition
From: |
Thomas Huth |
Subject: |
[PULL 03/24] target/s390x: Implement Early Exception Recognition |
Date: |
Mon, 20 Mar 2023 14:03:09 +0100 |
From: Ilya Leoshkevich <iii@linux.ibm.com>
Generate a specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addressing
mode.
Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20230315020408.384766-3-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
target/s390x/cpu.h | 1 +
target/s390x/cpu.c | 26 ++++++++++++++++++++++++++
target/s390x/tcg/excp_helper.c | 3 ++-
target/s390x/tcg/translate.c | 16 ++++++++++++++++
4 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 7d6d01325b..16f6354751 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -292,6 +292,7 @@ extern const VMStateDescription vmstate_s390_cpu;
#define PSW_MASK_32 0x0000000080000000ULL
#define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL
#define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL
+#define PSW_MASK_RESERVED 0xb80800fe7fffffffULL
#undef PSW_ASC_PRIMARY
#undef PSW_ASC_ACCREG
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index b10a8541ff..40fdeaa905 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -41,6 +41,26 @@
#define CR0_RESET 0xE0UL
#define CR14_RESET 0xC2000000UL;
+#ifndef CONFIG_USER_ONLY
+static bool is_early_exception_psw(uint64_t mask, uint64_t addr)
+{
+ if (mask & PSW_MASK_RESERVED) {
+ return true;
+ }
+
+ switch (mask & (PSW_MASK_32 | PSW_MASK_64)) {
+ case 0:
+ return addr & ~0xffffffULL;
+ case PSW_MASK_32:
+ return addr & ~0x7fffffffULL;
+ case PSW_MASK_32 | PSW_MASK_64:
+ return false;
+ default: /* PSW_MASK_64 */
+ return true;
+ }
+}
+#endif
+
void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
{
#ifndef CONFIG_USER_ONLY
@@ -57,6 +77,12 @@ void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask,
uint64_t addr)
env->cc_op = (mask >> 44) & 3;
#ifndef CONFIG_USER_ONLY
+ if (is_early_exception_psw(mask, addr)) {
+ env->int_pgm_ilen = 0;
+ trigger_pgm_exception(env, PGM_SPECIFICATION);
+ return;
+ }
+
if ((old_mask ^ mask) & PSW_MASK_PER) {
s390_cpu_recompute_watchpoints(env_cpu(env));
}
diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
index bc767f0443..a7829b1e49 100644
--- a/target/s390x/tcg/excp_helper.c
+++ b/target/s390x/tcg/excp_helper.c
@@ -212,7 +212,8 @@ static void do_program_interrupt(CPUS390XState *env)
LowCore *lowcore;
int ilen = env->int_pgm_ilen;
- assert(ilen == 2 || ilen == 4 || ilen == 6);
+ assert((env->int_pgm_code == PGM_SPECIFICATION && ilen == 0) ||
+ ilen == 2 || ilen == 4 || ilen == 6);
switch (env->int_pgm_code) {
case PGM_PER:
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 2e1e7e046a..7832cf02a6 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -4068,9 +4068,23 @@ static DisasJumpType op_sske(DisasContext *s, DisasOps
*o)
return DISAS_NEXT;
}
+static void gen_check_psw_mask(DisasContext *s)
+{
+ TCGv_i64 reserved = tcg_temp_new_i64();
+ TCGLabel *ok = gen_new_label();
+
+ tcg_gen_andi_i64(reserved, psw_mask, PSW_MASK_RESERVED);
+ tcg_gen_brcondi_i64(TCG_COND_EQ, reserved, 0, ok);
+ gen_program_exception(s, PGM_SPECIFICATION);
+ gen_set_label(ok);
+}
+
static DisasJumpType op_ssm(DisasContext *s, DisasOps *o)
{
tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
+
+ gen_check_psw_mask(s);
+
/* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
s->exit_to_mainloop = true;
return DISAS_TOO_MANY;
@@ -4331,6 +4345,8 @@ static DisasJumpType op_stnosm(DisasContext *s, DisasOps
*o)
tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
}
+ gen_check_psw_mask(s);
+
/* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
s->exit_to_mainloop = true;
return DISAS_TOO_MANY;
--
2.31.1
- [PULL 09/24] target/s390x: Handle branching to odd addresses, (continued)
- [PULL 09/24] target/s390x: Handle branching to odd addresses, Thomas Huth, 2023/03/20
- [PULL 08/24] tests/tcg/s390x: Add ex-relative-long.c, Thomas Huth, 2023/03/20
- [PULL 10/24] target/s390x: Handle EXECUTE of odd addresses, Thomas Huth, 2023/03/20
- [PULL 13/24] target/s390x: Handle LLGFRL from non-aligned addresses, Thomas Huth, 2023/03/20
- [PULL 11/24] target/s390x: Handle LGRL from non-aligned addresses, Thomas Huth, 2023/03/20
- [PULL 12/24] target/s390x: Handle LRL and LGFRL from non-aligned addresses, Thomas Huth, 2023/03/20
- [PULL 15/24] target/s390x: Handle CGRL and CLGRL with non-aligned addresses, Thomas Huth, 2023/03/20
- [PULL 02/24] target/s390x: Fix LPSW, Thomas Huth, 2023/03/20
- [PULL 14/24] target/s390x: Handle CRL and CGFRL with non-aligned addresses, Thomas Huth, 2023/03/20
- [PULL 21/24] target/s390x/tcg/mem_helper: Remove bad assert() statement, Thomas Huth, 2023/03/20
- [PULL 03/24] target/s390x: Implement Early Exception Recognition,
Thomas Huth <=
- [PULL 20/24] tests/tcg/s390x: Test unaligned accesses, Thomas Huth, 2023/03/20
- [PULL 19/24] target/s390x: Update do_unaligned_access() comment, Thomas Huth, 2023/03/20
- [PULL 24/24] replace TABs with spaces, Thomas Huth, 2023/03/20
- [PULL 17/24] target/s390x: Handle STRL to non-aligned addresses, Thomas Huth, 2023/03/20
- [PULL 16/24] target/s390x: Handle CLRL and CLGFRL with non-aligned addresses, Thomas Huth, 2023/03/20
- [PULL 23/24] qemu/osdep: Switch position of "extern" and "G_NORETURN", Thomas Huth, 2023/03/20
- [PULL 18/24] target/s390x: Handle STGRL to non-aligned addresses, Thomas Huth, 2023/03/20
- [PULL 22/24] tests/unit/test-blockjob: Disable complete_in_standby test, Thomas Huth, 2023/03/20
- Re: [PULL 00/24] s390x and misc patches for 8.0-rc1, Thomas Huth, 2023/03/20