Re: [RFC PATCH v2 15/44] target/loongarch: Implement vmul/vmuh/vmulw{ev/od}

[Richard Henderson]

On 3/27/23 20:06, Song Gao wrote:
> This patch includes:
> - VMUL.{B/H/W/D};
> - VMUH.{B/H/W/D}[U];
> - VMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
> - VMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
>   target/loongarch/disas.c                    |  38 ++
>   target/loongarch/helper.h                   |  36 ++
>   target/loongarch/insn_trans/trans_lsx.c.inc | 378 ++++++++++++++++++++
>   target/loongarch/insns.decode               |  38 ++
>   target/loongarch/lsx_helper.c               | 140 ++++++++
>   5 files changed, 630 insertions(+)
>
> diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
> index 6b0e518bfa..48e6ef5309 100644
> --- a/target/loongarch/disas.c
> +++ b/target/loongarch/disas.c
> @@ -972,3 +972,41 @@ INSN_LSX(vmini_bu,         vv_i)
>   INSN_LSX(vmini_hu,         vv_i)
>   INSN_LSX(vmini_wu,         vv_i)
>   INSN_LSX(vmini_du,         vv_i)
> +
> +INSN_LSX(vmul_b,           vvv)
> +INSN_LSX(vmul_h,           vvv)
> +INSN_LSX(vmul_w,           vvv)
> +INSN_LSX(vmul_d,           vvv)
> +INSN_LSX(vmuh_b,           vvv)
> +INSN_LSX(vmuh_h,           vvv)
> +INSN_LSX(vmuh_w,           vvv)
> +INSN_LSX(vmuh_d,           vvv)
> +INSN_LSX(vmuh_bu,          vvv)
> +INSN_LSX(vmuh_hu,          vvv)
> +INSN_LSX(vmuh_wu,          vvv)
> +INSN_LSX(vmuh_du,          vvv)
> +
> +INSN_LSX(vmulwev_h_b,      vvv)
> +INSN_LSX(vmulwev_w_h,      vvv)
> +INSN_LSX(vmulwev_d_w,      vvv)
> +INSN_LSX(vmulwev_q_d,      vvv)
> +INSN_LSX(vmulwod_h_b,      vvv)
> +INSN_LSX(vmulwod_w_h,      vvv)
> +INSN_LSX(vmulwod_d_w,      vvv)
> +INSN_LSX(vmulwod_q_d,      vvv)
> +INSN_LSX(vmulwev_h_bu,     vvv)
> +INSN_LSX(vmulwev_w_hu,     vvv)
> +INSN_LSX(vmulwev_d_wu,     vvv)
> +INSN_LSX(vmulwev_q_du,     vvv)
> +INSN_LSX(vmulwod_h_bu,     vvv)
> +INSN_LSX(vmulwod_w_hu,     vvv)
> +INSN_LSX(vmulwod_d_wu,     vvv)
> +INSN_LSX(vmulwod_q_du,     vvv)
> +INSN_LSX(vmulwev_h_bu_b,   vvv)
> +INSN_LSX(vmulwev_w_hu_h,   vvv)
> +INSN_LSX(vmulwev_d_wu_w,   vvv)
> +INSN_LSX(vmulwev_q_du_d,   vvv)
> +INSN_LSX(vmulwod_h_bu_b,   vvv)
> +INSN_LSX(vmulwod_w_hu_h,   vvv)
> +INSN_LSX(vmulwod_d_wu_w,   vvv)
> +INSN_LSX(vmulwod_q_du_d,   vvv)
> diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
> index f0fc7760bd..437b47fa78 100644
> --- a/target/loongarch/helper.h
> +++ b/target/loongarch/helper.h
> @@ -246,3 +246,39 @@ DEF_HELPER_FLAGS_4(vmaxi_bu, TCG_CALL_NO_RWG, void, ptr, 
> ptr, i64, i32)
>   DEF_HELPER_FLAGS_4(vmaxi_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
>   DEF_HELPER_FLAGS_4(vmaxi_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
>   DEF_HELPER_FLAGS_4(vmaxi_du, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
> +
> +DEF_HELPER_FLAGS_4(vmuh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmuh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmuh_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmuh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmuh_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmuh_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmuh_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmuh_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +
> +DEF_HELPER_FLAGS_4(vmulwev_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwev_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwev_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwev_q_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwod_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwod_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwod_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwod_q_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +
> +DEF_HELPER_FLAGS_4(vmulwev_h_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwev_w_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwev_d_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwev_q_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwod_h_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwod_w_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwod_d_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwod_q_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +
> +DEF_HELPER_FLAGS_4(vmulwev_h_bu_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwev_w_hu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwev_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwev_q_du_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwod_h_bu_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwod_w_hu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwod_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(vmulwod_q_du_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc 
> b/target/loongarch/insn_trans/trans_lsx.c.inc
> index 4e2f1ff097..583b608cd2 100644
> --- a/target/loongarch/insn_trans/trans_lsx.c.inc
> +++ b/target/loongarch/insn_trans/trans_lsx.c.inc
> @@ -1533,3 +1533,381 @@ TRANS(vmaxi_bu, gvec_vv_i, MO_8, do_vmaxi_u)
>   TRANS(vmaxi_hu, gvec_vv_i, MO_16, do_vmaxi_u)
>   TRANS(vmaxi_wu, gvec_vv_i, MO_32, do_vmaxi_u)
>   TRANS(vmaxi_du, gvec_vv_i, MO_64, do_vmaxi_u)
> +
> +TRANS(vmul_b, gvec_vvv, MO_8, tcg_gen_gvec_mul)
> +TRANS(vmul_h, gvec_vvv, MO_16, tcg_gen_gvec_mul)
> +TRANS(vmul_w, gvec_vvv, MO_32, tcg_gen_gvec_mul)
> +TRANS(vmul_d, gvec_vvv, MO_64, tcg_gen_gvec_mul)
> +
> +static void do_vmuh_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
> +                      uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
> +{
> +    static const GVecGen3 op[4] = {
> +        {
> +            .fno = gen_helper_vmuh_b,
> +            .vece = MO_8
> +        },
> +        {
> +            .fno = gen_helper_vmuh_h,
> +            .vece = MO_16
> +        },
> +        {
> +            .fno = gen_helper_vmuh_w,
> +            .vece = MO_32
> +        },
> +        {
> +            .fno = gen_helper_vmuh_d,
> +            .vece = MO_64
> +        },
> +    };

Could be worth integer expansion, especially for MO_32/MO_64?
Should be trivial...

> +static void do_vmulwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
> +                         uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
> +{
> +    static const TCGOpcode vecop_list[] = {
> +        INDEX_op_shli_vec, INDEX_op_sari_vec, INDEX_op_mul_vec, 0
> +        };
> +    static const GVecGen3 op[4] = {
> +        {
> +            .fniv = gen_vmulwev_s,
> +            .fno = gen_helper_vmulwev_h_b,
> +            .opt_opc = vecop_list,
> +            .vece = MO_16
> +        },
> +        {
> +            .fniv = gen_vmulwev_s,
> +            .fno = gen_helper_vmulwev_w_h,
> +            .opt_opc = vecop_list,
> +            .vece = MO_32
> +        },
> +        {
> +            .fniv = gen_vmulwev_s,
> +            .fno = gen_helper_vmulwev_d_w,
> +            .opt_opc = vecop_list,
> +            .vece = MO_64
> +        },
> +        {
> +            .fno = gen_helper_vmulwev_q_d,
> +            .vece = MO_128
> +        },
> +    };

Likewise.  And MO_128 may be had via tcg_gen_muls2_i64.

> +static void do_vmulwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
> +                         uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
> +{
> +    static const TCGOpcode vecop_list[] = {
> +        INDEX_op_shli_vec, INDEX_op_shri_vec, INDEX_op_mul_vec, 0
> +        };
> +    static const GVecGen3 op[4] = {
> +        {
> +            .fniv = gen_vmulwev_u,
> +            .fno = gen_helper_vmulwev_h_bu,
> +            .opt_opc = vecop_list,
> +            .vece = MO_16
> +        },
> +        {
> +            .fniv = gen_vmulwev_u,
> +            .fno = gen_helper_vmulwev_w_hu,
> +            .opt_opc = vecop_list,
> +            .vece = MO_32
> +        },
> +        {
> +            .fniv = gen_vmulwev_u,
> +            .fno = gen_helper_vmulwev_d_wu,
> +            .opt_opc = vecop_list,
> +            .vece = MO_64
> +        },
> +        {
> +            .fno = gen_helper_vmulwev_q_du,
> +            .vece = MO_128
> +        },
> +    };

tcg_gen_mulu2_i64.


r~