Re: [PATCH v2 3/6] target/ppc: Fix instruction loading endianness in alignment interrupt

[Fabiano Rosas]

Nicholas Piggin <npiggin@gmail.com> writes:

> powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
> after cpu_ldl_code(). This corrects DSISR bits in alignment
> interrupts when running in little endian mode.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

Reviewed-by: Fabiano Rosas <farosas@suse.de>