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[Qemu-ppc] [PATCH 06/19] openpic: combine mpic and openpic irq raise fun
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PATCH 06/19] openpic: combine mpic and openpic irq raise functions |
Date: |
Sat, 8 Dec 2012 14:44:29 +0100 |
The IRQ raise mechanisms of the OpenPIC and MPIC controllers is identical,
just that the MPIC one can also raise critical interrupts.
Combine those two and check for critical raise capability during runtime.
Signed-off-by: Alexander Graf <address@hidden>
---
hw/openpic.c | 34 ++++++++++++++++------------------
hw/openpic.h | 3 +++
2 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 29caa20..021bcea 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -206,6 +206,9 @@ typedef struct openpic_t {
PCIDevice pci_dev;
MemoryRegion mem;
+ /* Behavior control */
+ uint32_t flags;
+
/* Sub-regions */
MemoryRegion sub_io_mem[7];
@@ -233,9 +236,10 @@ typedef struct openpic_t {
int irq_ipi0;
int irq_tim0;
void (*reset) (void *);
- void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
} openpic_t;
+static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src);
+
static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
{
set_bit(q->queue, n_IRQ);
@@ -320,7 +324,7 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int
n_IRQ)
return;
}
DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ);
- opp->irq_raise(opp, n_CPU, src);
+ openpic_irq_raise(opp, n_CPU, src);
}
/* update pic state because registers for n_IRQ have changed value */
@@ -752,7 +756,7 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr
addr,
IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) {
DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
idx, n_IRQ);
- opp->irq_raise(opp, idx, src);
+ openpic_irq_raise(opp, idx, src);
}
break;
default:
@@ -995,7 +999,13 @@ static int openpic_load(QEMUFile* f, void *opaque, int
version_id)
static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
{
- qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
+ int n_ci = IDR_CI0 - n_CPU;
+
+ if ((opp->flags & OPENPIC_FLAG_IDE_CRIT) && test_bit(&src->ide, n_ci)) {
+ qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
+ } else {
+ qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
+ }
}
qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
@@ -1058,7 +1068,6 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
openpic_save, openpic_load, opp);
qemu_register_reset(openpic_reset, opp);
- opp->irq_raise = openpic_irq_raise;
opp->reset = openpic_reset;
if (pmem)
@@ -1067,18 +1076,6 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
}
-static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src)
-{
- int n_ci = IDR_CI0 - n_CPU;
-
- if(test_bit(&src->ide, n_ci)) {
- qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
- }
- else {
- qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
- }
-}
-
static void mpic_reset (void *opaque)
{
openpic_t *mpp = (openpic_t *)opaque;
@@ -1264,7 +1261,8 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr
base,
mpp->dst[i].irqs = irqs[i];
mpp->irq_out = irq_out;
- mpp->irq_raise = mpic_irq_raise;
+ /* Enable critical interrupt support */
+ mpp->flags |= OPENPIC_FLAG_IDE_CRIT;
mpp->reset = mpic_reset;
register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp);
diff --git a/hw/openpic.h b/hw/openpic.h
index f50a1e4..1232d10 100644
--- a/hw/openpic.h
+++ b/hw/openpic.h
@@ -11,6 +11,9 @@ enum {
OPENPIC_OUTPUT_NB,
};
+/* OpenPIC capability flags */
+#define OPENPIC_FLAG_IDE_CRIT (1 << 0)
+
qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out);
qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
--
1.6.0.2
- Re: [Qemu-ppc] [PATCH 19/19] MSI-X: Fix endianness, (continued)
- [Qemu-ppc] [PATCH 08/19] openpic: combine openpic and mpic reset functions, Alexander Graf, 2012/12/08
- [Qemu-ppc] [PATCH 13/19] openpic: remove irq_out, Alexander Graf, 2012/12/08
- [Qemu-ppc] [PATCH 05/19] openpic: Convert subregions to memory api, Alexander Graf, 2012/12/08
- [Qemu-ppc] [PATCH 17/19] PPC: e500: Add MSI support, Alexander Graf, 2012/12/08
- [Qemu-ppc] [PATCH 01/19] openpic: Remove unused code, Alexander Graf, 2012/12/08
- [Qemu-ppc] [PATCH 07/19] openpic: merge mpic and openpic timer handling, Alexander Graf, 2012/12/08
- [Qemu-ppc] [PATCH 06/19] openpic: combine mpic and openpic irq raise functions,
Alexander Graf <=
- [Qemu-ppc] [PATCH 16/19] openpic: add Shared MSI support, Alexander Graf, 2012/12/08
- Re: [Qemu-ppc] [PATCH 16/19] openpic: add Shared MSI support, Scott Wood, 2012/12/10
- Re: [Qemu-ppc] [PATCH 16/19] openpic: add Shared MSI support, Alexander Graf, 2012/12/11
- Re: [Qemu-ppc] [PATCH 16/19] openpic: add Shared MSI support, Scott Wood, 2012/12/11
- Re: [Qemu-ppc] [PATCH 16/19] openpic: add Shared MSI support, Alexander Graf, 2012/12/11
- Re: [Qemu-ppc] [PATCH 16/19] openpic: add Shared MSI support, Scott Wood, 2012/12/11
- Re: [Qemu-ppc] [PATCH 16/19] openpic: add Shared MSI support, Alexander Graf, 2012/12/12
[Qemu-ppc] [PATCH 02/19] mpic: Unify numbering scheme, Alexander Graf, 2012/12/08