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[Qemu-ppc] [PULL 37/66] ppc: Don't update NIP in dcbz and lscbx
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 37/66] ppc: Don't update NIP in dcbz and lscbx |
Date: |
Tue, 6 Sep 2016 13:42:47 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
Instead, pass GETPC() result to the corresponding helpers.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/mem_helper.c | 9 +++++----
target-ppc/translate.c | 4 ----
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index e20a53e..92a594c 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -141,13 +141,14 @@ void helper_stsw(CPUPPCState *env, target_ulong addr,
uint32_t nb,
}
}
-static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size)
+static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size,
+ uintptr_t raddr)
{
int i;
addr &= ~(dcache_line_size - 1);
for (i = 0; i < dcache_line_size; i += 4) {
- cpu_stl_data(env, addr + i, 0);
+ cpu_stl_data_ra(env, addr + i, 0, raddr);
}
if (env->reserve_addr == addr) {
env->reserve_addr = (target_ulong)-1ULL;
@@ -168,7 +169,7 @@ void helper_dcbz(CPUPPCState *env, target_ulong addr,
uint32_t is_dcbzl)
/* XXX add e500mc support */
- do_dcbz(env, addr, dcbz_size);
+ do_dcbz(env, addr, dcbz_size, GETPC());
}
void helper_icbi(CPUPPCState *env, target_ulong addr)
@@ -190,7 +191,7 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong
addr, uint32_t reg,
d = 24;
for (i = 0; i < xer_bc; i++) {
- c = cpu_ldub_data(env, addr);
+ c = cpu_ldub_data_ra(env, addr, GETPC());
addr = addr_add(env, addr, 1);
/* ra (if not 0) and rb are never modified */
if (likely(reg != rb && (ra == 0 || reg != ra))) {
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6320ae5..bebd1cc 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -4055,8 +4055,6 @@ static void gen_dcbz(DisasContext *ctx)
int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
gen_set_access_type(ctx, ACCESS_CACHE);
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
tcgv_addr = tcg_temp_new();
tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
@@ -4584,8 +4582,6 @@ static void gen_lscbx(DisasContext *ctx)
TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
gen_addr_reg_index(ctx, t0);
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
--
2.7.4
- [Qemu-ppc] [PULL 09/66] target-ppc: add cnttzd[.] instruction, (continued)
- [Qemu-ppc] [PULL 09/66] target-ppc: add cnttzd[.] instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 23/66] ppc: Make float_invalid_op_excp() pass the return address, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 06/66] target-ppc: add cmprb instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 15/66] target-ppc: introduce opc4 for Expanded Opcode, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 12/66] target-ppc: add setb instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 14/66] target-ppc: add maddhd and maddhdu instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 08/66] target-ppc: add modulo dword operations, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 02/66] hw/ppc: include fdt helper routine in a common file, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 16/66] ppc: Provide basic raise_exception_* functions, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 44/66] ppc: load/store multiple and string insns don't do LE, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 37/66] ppc: Don't update NIP in dcbz and lscbx,
David Gibson <=
- [Qemu-ppc] [PULL 10/66] target-ppc: add cnttzw[.] instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 28/66] ppc: Don't update NIP in lmw/stmw/icbi, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 24/66] ppc: Make float_check_status() pass the return address, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 43/66] ppc: Use a helper to generate "LE unsupported" alignment interrupts, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 27/66] ppc: Don't update NIP in lswi/lswx/stswi/stswx, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 46/66] target-ppc: implement branch-less divw[o][.], David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 39/66] ppc: Handle unconditional (always/never) traps at translation time, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 42/66] ppc: Don't set access_type on all load/stores on hash64, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 36/66] ppc: Don't update NIP if not taking alignment exceptions, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 57/66] ppc: Fix macio ESCC legacy mapping, David Gibson, 2016/09/05