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[PULL 67/87] ppc/pnv: Add support for PHB5 "Address-based trigger" mode
From: |
Cédric Le Goater |
Subject: |
[PULL 67/87] ppc/pnv: Add support for PHB5 "Address-based trigger" mode |
Date: |
Wed, 2 Mar 2022 12:07:43 +0100 |
When the Address-Based Interrupt Trigger mode is activated, the PHB
maps the interrupt source number into the interrupt command address.
The PHB directly triggers the IC ESB page of the interrupt number and
not the notify page of the IC anymore.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/pci-host/pnv_phb4_regs.h | 2 +
hw/pci-host/pnv_phb4.c | 73 ++++++++++++++++++++++++++---
hw/pci-host/trace-events | 2 +
3 files changed, 71 insertions(+), 6 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb4_regs.h
b/include/hw/pci-host/pnv_phb4_regs.h
index 64f326b7158e..4a0d3b28efb3 100644
--- a/include/hw/pci-host/pnv_phb4_regs.h
+++ b/include/hw/pci-host/pnv_phb4_regs.h
@@ -220,12 +220,14 @@
#define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16, 63)
#define PHB_ETU_ERR_SUMMARY 0x2c8
#define PHB_INT_NOTIFY_ADDR 0x300
+#define PHB_INT_NOTIFY_ADDR_64K PPC_BIT(1) /* P10 */
#define PHB_INT_NOTIFY_INDEX 0x308
/* Fundamental register set B */
#define PHB_VERSION 0x800
#define PHB_CTRLR 0x810
#define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* P10 */
+#define PHB_CTRLR_IRQ_ABT_MODE PPC_BIT(10) /* P10 */
#define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11)
#define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12)
#define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 0b407ac69ba6..b5b384e9ee4f 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1669,10 +1669,54 @@ static const char *pnv_phb4_root_bus_path(PCIHostState
*host_bridge,
return phb->bus_path;
}
-static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,
- bool pq_checked)
+/*
+ * Address base trigger mode (POWER10)
+ *
+ * Trigger directly the IC ESB page
+ */
+static void pnv_phb4_xive_notify_abt(PnvPHB4 *phb, uint32_t srcno,
+ bool pq_checked)
+{
+ uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3];
+ uint64_t data = 0; /* trigger data : don't care */
+ hwaddr addr;
+ MemTxResult result;
+ int esb_shift;
+
+ if (notif_port & PHB_INT_NOTIFY_ADDR_64K) {
+ esb_shift = 16;
+ } else {
+ esb_shift = 12;
+ }
+
+ /* Compute the address of the IC ESB management page */
+ addr = (notif_port & ~PHB_INT_NOTIFY_ADDR_64K);
+ addr |= (1ull << (esb_shift + 1)) * srcno;
+ addr |= (1ull << esb_shift);
+
+ /*
+ * When the PQ state bits are checked on the PHB, the associated
+ * PQ state bits on the IC should be ignored. Use the unconditional
+ * trigger offset to inject a trigger on the IC. This is always
+ * the case for LSIs
+ */
+ if (pq_checked) {
+ addr |= XIVE_ESB_INJECT;
+ }
+
+ trace_pnv_phb4_xive_notify_ic(addr, data);
+
+ address_space_stq_be(&address_space_memory, addr, data,
+ MEMTXATTRS_UNSPECIFIED, &result);
+ if (result != MEMTX_OK) {
+ phb_error(phb, "trigger failed @%"HWADDR_PRIx "\n", addr);
+ return;
+ }
+}
+
+static void pnv_phb4_xive_notify_ic(PnvPHB4 *phb, uint32_t srcno,
+ bool pq_checked)
{
- PnvPHB4 *phb = PNV_PHB4(xf);
uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3];
uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3];
uint64_t data = offset | srcno;
@@ -1682,7 +1726,7 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf,
uint32_t srcno,
data |= XIVE_TRIGGER_PQ;
}
- trace_pnv_phb4_xive_notify(notif_port, data);
+ trace_pnv_phb4_xive_notify_ic(notif_port, data);
address_space_stq_be(&address_space_memory, notif_port, data,
MEMTXATTRS_UNSPECIFIED, &result);
@@ -1692,6 +1736,18 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf,
uint32_t srcno,
}
}
+static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,
+ bool pq_checked)
+{
+ PnvPHB4 *phb = PNV_PHB4(xf);
+
+ if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE) {
+ pnv_phb4_xive_notify_abt(phb, srcno, pq_checked);
+ } else {
+ pnv_phb4_xive_notify_ic(phb, srcno, pq_checked);
+ }
+}
+
static Property pnv_phb4_properties[] = {
DEFINE_PROP_UINT32("index", PnvPHB4, phb_id, 0),
DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
@@ -1858,10 +1914,15 @@ type_init(pnv_phb4_register_types);
void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon)
{
+ uint64_t notif_port =
+ phb->regs[PHB_INT_NOTIFY_ADDR >> 3] & ~PHB_INT_NOTIFY_ADDR_64K;
uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3];
+ bool abt = !!(phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE);
- monitor_printf(mon, "PHB4[%x:%x] Source %08x .. %08x\n",
+ monitor_printf(mon, "PHB4[%x:%x] Source %08x .. %08x %s @%"HWADDR_PRIx"\n",
phb->chip_id, phb->phb_id,
- offset, offset + phb->xsrc.nr_irqs - 1);
+ offset, offset + phb->xsrc.nr_irqs - 1,
+ abt ? "ABT" : "",
+ notif_port);
xive_source_pic_print_info(&phb->xsrc, 0, mon);
}
diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
index 630e9fcc5e77..6e5d8d335525 100644
--- a/hw/pci-host/trace-events
+++ b/hw/pci-host/trace-events
@@ -32,3 +32,5 @@ unin_read(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 "
val=0x%"PRIx64
# pnv_phb4.c
pnv_phb4_xive_notify(uint64_t notif_port, uint64_t data) "notif=@0x%"PRIx64"
data=0x%"PRIx64
+pnv_phb4_xive_notify_ic(uint64_t addr, uint64_t data) "addr=@0x%"PRIx64"
data=0x%"PRIx64
+pnv_phb4_xive_notify_abt(uint64_t notif_port, uint64_t data)
"notif=@0x%"PRIx64" data=0x%"PRIx64
--
2.34.1
- [PULL 53/87] target/ppc: implement plxsd/pstxsd, (continued)
- [PULL 53/87] target/ppc: implement plxsd/pstxsd, Cédric Le Goater, 2022/03/02
- [PULL 48/87] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree, Cédric Le Goater, 2022/03/02
- [PULL 43/87] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o], Cédric Le Goater, 2022/03/02
- [PULL 76/87] hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_set_string(), Cédric Le Goater, 2022/03/02
- [PULL 74/87] hw/ppc/spapr.c: use g_autofree in spapr_dt_chosen(), Cédric Le Goater, 2022/03/02
- [PULL 44/87] target/ppc: Implement xvtlsbb instruction, Cédric Le Goater, 2022/03/02
- [PULL 75/87] hw/ppc/spapr.c: fail early if no firmware found in machine_init(), Cédric Le Goater, 2022/03/02
- [PULL 77/87] hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_get_string(), Cédric Le Goater, 2022/03/02
- [PULL 80/87] hw/ppc/spapr_drc.c: use g_autofree in drc_realize(), Cédric Le Goater, 2022/03/02
- [PULL 62/87] ppc/pnv: Add a HOMER model to POWER10, Cédric Le Goater, 2022/03/02
- [PULL 67/87] ppc/pnv: Add support for PHB5 "Address-based trigger" mode,
Cédric Le Goater <=
- [PULL 68/87] pnv/xive2: Introduce new capability bits, Cédric Le Goater, 2022/03/02
- [PULL 60/87] ppc/pnv: Add POWER10 quads, Cédric Le Goater, 2022/03/02
- [PULL 70/87] pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1), Cédric Le Goater, 2022/03/02
- [PULL 69/87] ppc/pnv: add XIVE Gen2 TIMA support, Cédric Le Goater, 2022/03/02
- [PULL 61/87] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge, Cédric Le Goater, 2022/03/02
- [PULL 72/87] pnv/xive2: Add support for automatic save&restore, Cédric Le Goater, 2022/03/02
- [PULL 71/87] xive2: Add a get_config() handler for the router configuration, Cédric Le Goater, 2022/03/02
- [PULL 79/87] hw/ppc/spapr_drc.c: use g_auto in spapr_dt_drc(), Cédric Le Goater, 2022/03/02
- [PULL 85/87] spapr_pci_nvlink2.c: use g_autofree in spapr_phb_nvgpu_ram_populate_dt(), Cédric Le Goater, 2022/03/02
- [PULL 84/87] hw/ppc/spapr_numa.c: simplify spapr_numa_write_assoc_lookup_arrays(), Cédric Le Goater, 2022/03/02