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[PULL 68/87] pnv/xive2: Introduce new capability bits
From: |
Cédric Le Goater |
Subject: |
[PULL 68/87] pnv/xive2: Introduce new capability bits |
Date: |
Wed, 2 Mar 2022 12:07:44 +0100 |
These bits control the availability of interrupt features : StoreEOI,
PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE
exploitation mode. These bits can be set at early boot time of the
system to activate/deactivate a feature for testing purposes. The
default value should be '1'.
The 'XIVE exploitation mode' bit is a software bit that skiboot could
use to disable the XIVE OS interface and propose a P8 style XICS
interface instead. There are no plans for that for the moment.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/intc/pnv_xive2_regs.h | 5 +++++
hw/intc/pnv_xive2.c | 4 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h
index d45d17cedcca..a46e5133b560 100644
--- a/hw/intc/pnv_xive2_regs.h
+++ b/hw/intc/pnv_xive2_regs.h
@@ -31,6 +31,11 @@
#define CQ_XIVE_CAP_VP_INT_PRIO_8 3
#define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13)
+#define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56)
+#define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57)
+#define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58)
+#define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59)
+
/* XIVE2 Configuration */
#define X_CQ_XIVE_CFG 0x03
#define CQ_XIVE_CFG 0x018
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 1fa89c779287..e22049424f37 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -1709,9 +1709,9 @@ static const MemoryRegionOps pnv_xive2_nvpg_ops = {
};
/*
- * POWER10 default capabilities: 0x2000120076f00000
+ * POWER10 default capabilities: 0x2000120076f000FC
*/
-#define PNV_XIVE2_CAPABILITIES 0x2000120076f00000
+#define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC
/*
* POWER10 default configuration: 0x0030000033000000
--
2.34.1
- [PULL 48/87] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree, (continued)
- [PULL 48/87] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree, Cédric Le Goater, 2022/03/02
- [PULL 43/87] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o], Cédric Le Goater, 2022/03/02
- [PULL 76/87] hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_set_string(), Cédric Le Goater, 2022/03/02
- [PULL 74/87] hw/ppc/spapr.c: use g_autofree in spapr_dt_chosen(), Cédric Le Goater, 2022/03/02
- [PULL 44/87] target/ppc: Implement xvtlsbb instruction, Cédric Le Goater, 2022/03/02
- [PULL 75/87] hw/ppc/spapr.c: fail early if no firmware found in machine_init(), Cédric Le Goater, 2022/03/02
- [PULL 77/87] hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_get_string(), Cédric Le Goater, 2022/03/02
- [PULL 80/87] hw/ppc/spapr_drc.c: use g_autofree in drc_realize(), Cédric Le Goater, 2022/03/02
- [PULL 62/87] ppc/pnv: Add a HOMER model to POWER10, Cédric Le Goater, 2022/03/02
- [PULL 67/87] ppc/pnv: Add support for PHB5 "Address-based trigger" mode, Cédric Le Goater, 2022/03/02
- [PULL 68/87] pnv/xive2: Introduce new capability bits,
Cédric Le Goater <=
- [PULL 60/87] ppc/pnv: Add POWER10 quads, Cédric Le Goater, 2022/03/02
- [PULL 70/87] pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1), Cédric Le Goater, 2022/03/02
- [PULL 69/87] ppc/pnv: add XIVE Gen2 TIMA support, Cédric Le Goater, 2022/03/02
- [PULL 61/87] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge, Cédric Le Goater, 2022/03/02
- [PULL 72/87] pnv/xive2: Add support for automatic save&restore, Cédric Le Goater, 2022/03/02
- [PULL 71/87] xive2: Add a get_config() handler for the router configuration, Cédric Le Goater, 2022/03/02
- [PULL 79/87] hw/ppc/spapr_drc.c: use g_auto in spapr_dt_drc(), Cédric Le Goater, 2022/03/02
- [PULL 85/87] spapr_pci_nvlink2.c: use g_autofree in spapr_phb_nvgpu_ram_populate_dt(), Cédric Le Goater, 2022/03/02
- [PULL 84/87] hw/ppc/spapr_numa.c: simplify spapr_numa_write_assoc_lookup_arrays(), Cédric Le Goater, 2022/03/02
- [PULL 81/87] hw/ppc/spapr_drc.c: use g_autofree in drc_unrealize(), Cédric Le Goater, 2022/03/02