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[PULL 57/62] target/ppc: Increment PMC5 with inline insns
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 57/62] target/ppc: Increment PMC5 with inline insns |
Date: |
Fri, 28 Oct 2022 13:39:46 -0300 |
From: Leandro Lupori <leandro.lupori@eldorado.org.br>
Profiling QEMU during Fedora 35 for PPC64 boot revealed that
6.39% of total time was being spent in helper_insns_inc(), on a
POWER9 machine. To avoid calling this helper every time PMCs had
to be incremented, an inline implementation of PMC5 increment and
check for overflow was developed. This led to a reduction of
about 12% in Fedora's boot time.
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221025202424.195984-4-leandro.lupori@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/helper.h | 1 +
target/ppc/power8-pmu.c | 74 +++++++++++++++++++++--------------------
target/ppc/power8-pmu.h | 3 ++
target/ppc/translate.c | 28 ++++++++++++++--
4 files changed, 67 insertions(+), 39 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 25533b8f33..8dd22a35e4 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -30,6 +30,7 @@ DEF_HELPER_2(store_mmcr1, void, env, tl)
DEF_HELPER_3(store_pmc, void, env, i32, i64)
DEF_HELPER_2(read_pmc, tl, env, i32)
DEF_HELPER_2(insns_inc, void, env, i32)
+DEF_HELPER_1(handle_pmc5_overflow, void, env)
#endif
DEF_HELPER_1(check_tlb_flush_local, void, env)
DEF_HELPER_1(check_tlb_flush_global, void, env)
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index beeab5c494..1381072b9e 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -22,8 +22,6 @@
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL
-
static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn)
{
if (sprn == SPR_POWER_PMC1) {
@@ -88,49 +86,47 @@ static bool pmu_increment_insns(CPUPPCState *env, uint32_t
num_insns)
bool overflow_triggered = false;
target_ulong tmp;
- if (unlikely(ins_cnt & 0x1e)) {
- if (ins_cnt & (1 << 1)) {
- tmp = env->spr[SPR_POWER_PMC1];
- tmp += num_insns;
- if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMC1CE)) {
- tmp = PMC_COUNTER_NEGATIVE_VAL;
- overflow_triggered = true;
- }
- env->spr[SPR_POWER_PMC1] = tmp;
+ if (ins_cnt & (1 << 1)) {
+ tmp = env->spr[SPR_POWER_PMC1];
+ tmp += num_insns;
+ if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMC1CE)) {
+ tmp = PMC_COUNTER_NEGATIVE_VAL;
+ overflow_triggered = true;
}
+ env->spr[SPR_POWER_PMC1] = tmp;
+ }
- if (ins_cnt & (1 << 2)) {
- tmp = env->spr[SPR_POWER_PMC2];
- tmp += num_insns;
- if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) {
- tmp = PMC_COUNTER_NEGATIVE_VAL;
- overflow_triggered = true;
- }
- env->spr[SPR_POWER_PMC2] = tmp;
+ if (ins_cnt & (1 << 2)) {
+ tmp = env->spr[SPR_POWER_PMC2];
+ tmp += num_insns;
+ if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) {
+ tmp = PMC_COUNTER_NEGATIVE_VAL;
+ overflow_triggered = true;
+ }
+ env->spr[SPR_POWER_PMC2] = tmp;
+ }
+
+ if (ins_cnt & (1 << 3)) {
+ tmp = env->spr[SPR_POWER_PMC3];
+ tmp += num_insns;
+ if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) {
+ tmp = PMC_COUNTER_NEGATIVE_VAL;
+ overflow_triggered = true;
}
+ env->spr[SPR_POWER_PMC3] = tmp;
+ }
- if (ins_cnt & (1 << 3)) {
- tmp = env->spr[SPR_POWER_PMC3];
+ if (ins_cnt & (1 << 4)) {
+ target_ulong mmcr1 = env->spr[SPR_POWER_MMCR1];
+ int sel = extract64(mmcr1, MMCR1_PMC4EVT_EXTR, MMCR1_EVT_SIZE);
+ if (sel == 0x02 || (env->spr[SPR_CTRL] & CTRL_RUN)) {
+ tmp = env->spr[SPR_POWER_PMC4];
tmp += num_insns;
if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) {
tmp = PMC_COUNTER_NEGATIVE_VAL;
overflow_triggered = true;
}
- env->spr[SPR_POWER_PMC3] = tmp;
- }
-
- if (ins_cnt & (1 << 4)) {
- target_ulong mmcr1 = env->spr[SPR_POWER_MMCR1];
- int sel = extract64(mmcr1, MMCR1_PMC4EVT_EXTR, MMCR1_EVT_SIZE);
- if (sel == 0x02 || (env->spr[SPR_CTRL] & CTRL_RUN)) {
- tmp = env->spr[SPR_POWER_PMC4];
- tmp += num_insns;
- if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE))
{
- tmp = PMC_COUNTER_NEGATIVE_VAL;
- overflow_triggered = true;
- }
- env->spr[SPR_POWER_PMC4] = tmp;
- }
+ env->spr[SPR_POWER_PMC4] = tmp;
}
}
@@ -310,6 +306,12 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu)
raise_ebb_perfm_exception(env);
}
+void helper_handle_pmc5_overflow(CPUPPCState *env)
+{
+ env->spr[SPR_POWER_PMC5] = PMC_COUNTER_NEGATIVE_VAL;
+ fire_PMC_interrupt(env_archcpu(env));
+}
+
/* This helper assumes that the PMC is running. */
void helper_insns_inc(CPUPPCState *env, uint32_t num_insns)
{
diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h
index 9692dd765e..c0093e2219 100644
--- a/target/ppc/power8-pmu.h
+++ b/target/ppc/power8-pmu.h
@@ -14,6 +14,9 @@
#define POWER8_PMU_H
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+
+#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL
+
void cpu_ppc_pmu_init(CPUPPCState *env);
void pmu_update_summaries(CPUPPCState *env);
#else
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 8d79522f98..19c1d17cb0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -36,6 +36,7 @@
#include "exec/log.h"
#include "qemu/atomic128.h"
#include "spr_common.h"
+#include "power8-pmu.h"
#include "qemu/qemu-print.h"
#include "qapi/error.h"
@@ -4271,6 +4272,9 @@ static void pmu_count_insns(DisasContext *ctx)
}
#if !defined(CONFIG_USER_ONLY)
+ TCGLabel *l;
+ TCGv t0;
+
/*
* The PMU insns_inc() helper stops the internal PMU timer if a
* counter overflows happens. In that case, if the guest is
@@ -4279,8 +4283,26 @@ static void pmu_count_insns(DisasContext *ctx)
*/
gen_icount_io_start(ctx);
- gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns));
-#else
+ /* Avoid helper calls when only PMC5-6 are enabled. */
+ if (!ctx->pmc_other) {
+ l = gen_new_label();
+ t0 = tcg_temp_new();
+
+ gen_load_spr(t0, SPR_POWER_PMC5);
+ tcg_gen_addi_tl(t0, t0, ctx->base.num_insns);
+ gen_store_spr(SPR_POWER_PMC5, t0);
+ /* Check for overflow, if it's enabled */
+ if (ctx->mmcr0_pmcjce) {
+ tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l);
+ gen_helper_handle_pmc5_overflow(cpu_env);
+ }
+
+ gen_set_label(l);
+ tcg_temp_free(t0);
+ } else {
+ gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns));
+ }
+ #else
/*
* User mode can read (but not write) PMC5 and start/stop
* the PMU via MMCR0_FC. In this case just increment
@@ -4293,7 +4315,7 @@ static void pmu_count_insns(DisasContext *ctx)
gen_store_spr(SPR_POWER_PMC5, t0);
tcg_temp_free(t0);
-#endif /* #if !defined(CONFIG_USER_ONLY) */
+ #endif /* #if !defined(CONFIG_USER_ONLY) */
}
#else
static void pmu_count_insns(DisasContext *ctx)
--
2.37.3
- [PULL 47/62] target/ppc: move the p*_interrupt_powersave methods to excp_helper.c, (continued)
- [PULL 47/62] target/ppc: move the p*_interrupt_powersave methods to excp_helper.c, Daniel Henrique Barboza, 2022/10/28
- [PULL 48/62] ppc440_uc.c: Move DDR2 SDRAM controller model to ppc4xx_sdram.c, Daniel Henrique Barboza, 2022/10/28
- [PULL 50/62] ppc4xx_sdram: Move ppc4xx_sdram_banks() to ppc4xx_sdram.c, Daniel Henrique Barboza, 2022/10/28
- [PULL 49/62] ppc4xx_devs.c: Move DDR SDRAM controller model to ppc4xx_sdram.c, Daniel Henrique Barboza, 2022/10/28
- [PULL 51/62] ppc4xx_sdram: Use hwaddr for memory bank size, Daniel Henrique Barboza, 2022/10/28
- [PULL 52/62] ppc4xx_sdram: Rename local state variable for brevity, Daniel Henrique Barboza, 2022/10/28
- [PULL 53/62] ppc4xx_sdram: Generalise bank setup, Daniel Henrique Barboza, 2022/10/28
- [PULL 54/62] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling, Daniel Henrique Barboza, 2022/10/28
- [PULL 55/62] ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks(), Daniel Henrique Barboza, 2022/10/28
- [PULL 56/62] target/ppc: Add new PMC HFLAGS, Daniel Henrique Barboza, 2022/10/28
- [PULL 57/62] target/ppc: Increment PMC5 with inline insns,
Daniel Henrique Barboza <=
- [PULL 58/62] docs/system/ppc/ppce500: Use qemu-system-ppc64 across the board(s), Daniel Henrique Barboza, 2022/10/28
- [PULL 59/62] hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power of two, Daniel Henrique Barboza, 2022/10/28
- [PULL 60/62] hw/sd/sdhci-internal: Unexport ESDHC defines, Daniel Henrique Barboza, 2022/10/28
- [PULL 61/62] hw/sd/sdhci: Rename ESDHC_* defines to USDHC_*, Daniel Henrique Barboza, 2022/10/28
- [PULL 62/62] hw/ppc/e500: Implement pflash handling, Daniel Henrique Barboza, 2022/10/28
- Re: [PULL 00/62] ppc queue, Daniel Henrique Barboza, 2022/10/28