[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 03/15] hw/sd/sdhci: Support big endian SD host controller interfac
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 03/15] hw/sd/sdhci: Support big endian SD host controller interfaces |
Date: |
Tue, 20 Dec 2022 10:52:39 -0300 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Some SDHCI IP can be synthetized in various endianness:
https://github.com/u-boot/u-boot/blob/v2021.04/doc/README.fsl-esdhc
- CONFIG_SYS_FSL_ESDHC_BE
ESDHC IP is in big-endian mode. Accessing ESDHC registers can be
determined by ESDHC IP's endian mode or processor's endian mode.
Our current implementation is little-endian. In order to support
big endianness:
- Rename current MemoryRegionOps as sdhci_mmio_le_ops ('le')
- Add an 'endianness' property to SDHCIState (default little endian)
- Set the 'io_ops' field in realize() after checking the property
- Add the sdhci_mmio_be_ops (big-endian) MemoryRegionOps.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221101222934.52444-3-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/sd/sdhci-internal.h | 1 +
hw/sd/sdhci.c | 32 +++++++++++++++++++++++++++++---
include/hw/sd/sdhci.h | 1 +
3 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 964570f8e8..5f3765f12d 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -308,6 +308,7 @@ extern const VMStateDescription sdhci_vmstate;
#define SDHC_CAPAB_REG_DEFAULT 0x057834b4
#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
+ DEFINE_PROP_UINT8("endianness", _state, endianness, DEVICE_LITTLE_ENDIAN),
\
DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \
DEFINE_PROP_UINT8("vendor", _state, vendor, SDHCI_VENDOR_NONE), \
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 22c758ad91..289baa879e 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1329,7 +1329,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
value >> shift, value >> shift);
}
-static const MemoryRegionOps sdhci_mmio_ops = {
+static const MemoryRegionOps sdhci_mmio_le_ops = {
.read = sdhci_read,
.write = sdhci_write,
.impl = {
@@ -1344,6 +1344,21 @@ static const MemoryRegionOps sdhci_mmio_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
+static const MemoryRegionOps sdhci_mmio_be_ops = {
+ .read = sdhci_read,
+ .write = sdhci_write,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ .unaligned = false
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
{
ERRP_GUARD();
@@ -1371,8 +1386,6 @@ void sdhci_initfn(SDHCIState *s)
s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
sdhci_raise_insertion_irq, s);
s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer,
s);
-
- s->io_ops = &sdhci_mmio_ops;
}
void sdhci_uninitfn(SDHCIState *s)
@@ -1388,10 +1401,23 @@ void sdhci_common_realize(SDHCIState *s, Error **errp)
{
ERRP_GUARD();
+ switch (s->endianness) {
+ case DEVICE_LITTLE_ENDIAN:
+ s->io_ops = &sdhci_mmio_le_ops;
+ break;
+ case DEVICE_BIG_ENDIAN:
+ s->io_ops = &sdhci_mmio_be_ops;
+ break;
+ default:
+ error_setg(errp, "Incorrect endianness");
+ return;
+ }
+
sdhci_init_readonly_registers(s, errp);
if (*errp) {
return;
}
+
s->buf_maxsz = sdhci_get_fifolen(s);
s->fifo_buffer = g_malloc0(s->buf_maxsz);
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 01a64c5442..a989fca3b2 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -96,6 +96,7 @@ struct SDHCIState {
/* Configurable properties */
bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */
uint32_t quirks;
+ uint8_t endianness;
uint8_t sd_spec_version;
uint8_t uhs_mode;
uint8_t vendor; /* For vendor specific functionality */
--
2.38.1
- [PULL 00/15] ppc queue, Daniel Henrique Barboza, 2022/12/20
- [PULL 01/15] MAINTAINERS: downgrade PPC KVM/TCG CPUs and pSeries to 'Odd Fixes', Daniel Henrique Barboza, 2022/12/20
- [PULL 02/15] hw/sd/sdhci: MMIO region is implemented in 32-bit accesses, Daniel Henrique Barboza, 2022/12/20
- [PULL 03/15] hw/sd/sdhci: Support big endian SD host controller interfaces,
Daniel Henrique Barboza <=
- [PULL 04/15] hw/ppc/e500: Add Freescale eSDHC to e500plat, Daniel Henrique Barboza, 2022/12/20
- [PULL 05/15] target/ppc/kvm: Add missing "cpu.h" and "exec/hwaddr.h", Daniel Henrique Barboza, 2022/12/20
- [PULL 06/15] hw/ppc/vof: Do not include the full "cpu.h", Daniel Henrique Barboza, 2022/12/20
- [PULL 07/15] hw/ppc/spapr: Reduce "vof.h" inclusion, Daniel Henrique Barboza, 2022/12/20
- [PULL 08/15] target/ppc/mmu_common: Log which effective address had no TLB entry found, Daniel Henrique Barboza, 2022/12/20
- [PULL 09/15] target/ppc/mmu_common: Fix table layout of "info tlb" HMP command, Daniel Henrique Barboza, 2022/12/20
- [PULL 10/15] hw/ppc/virtex_ml507: Prefer local over global variable, Daniel Henrique Barboza, 2022/12/20
- [PULL 11/15] hw/ppc/e500: Prefer local variable over qdev_get_machine(), Daniel Henrique Barboza, 2022/12/20
- [PULL 12/15] hw/ppc/e500: Resolve variable shadowing, Daniel Henrique Barboza, 2022/12/20
- [PULL 13/15] hw/ppc/e500: Move comment to more appropriate place, Daniel Henrique Barboza, 2022/12/20