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[PATCH v3 4/9] target/ppc: Alignment faults do not set DSISR in ISA v3.0
From: |
Nicholas Piggin |
Subject: |
[PATCH v3 4/9] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward |
Date: |
Mon, 15 May 2023 19:26:50 +1000 |
This optional behavior was removed from the ISA in v3.0, see
Summary of Changes preface:
Data Storage Interrupt Status Register for Alignment Interrupt:
Simplifies the Alignment interrupt by remov- ing the Data Storage
Interrupt Status Register (DSISR) from the set of registers modified
by the Alignment interrupt.
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v2: no change.
target/ppc/excp_helper.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index bc2be4a726..453750a9d6 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1449,13 +1449,16 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int
excp)
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
- /* Get rS/rD and rA from faulting opcode */
- /*
- * Note: the opcode fields will not be set properly for a
- * direct store load/store, but nobody cares as nobody
- * actually uses direct store segments.
- */
- env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
+ /* Optional DSISR update was removed from ISA v3.0 */
+ if (!(env->insns_flags2 & PPC2_ISA300)) {
+ /* Get rS/rD and rA from faulting opcode */
+ /*
+ * Note: the opcode fields will not be set properly for a
+ * direct store load/store, but nobody cares as nobody
+ * actually uses direct store segments.
+ */
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
+ }
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
--
2.40.1
- Re: [PATCH v3 1/9] target/ppc: Fix width of some 32-bit SPRs, (continued)
[PATCH v3 2/9] target/ppc: Fix PMU MMCR0[PMCjCE] bit in hflags calculation, Nicholas Piggin, 2023/05/15
[PATCH v3 3/9] target/ppc: Fix instruction loading endianness in alignment interrupt, Nicholas Piggin, 2023/05/15
[PATCH v3 4/9] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward,
Nicholas Piggin <=
[PATCH v3 5/9] target/ppc: Change partition-scope translate interface, Nicholas Piggin, 2023/05/15
[PATCH v3 7/9] target/ppc: Implement HEIR SPR, Nicholas Piggin, 2023/05/15
[PATCH v3 8/9] target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts, Nicholas Piggin, 2023/05/15
[PATCH v3 6/9] target/ppc: Add SRR1 prefix indication to interrupt handlers, Nicholas Piggin, 2023/05/15
[PATCH v3 9/9] target/ppc: Better CTRL SPR implementation, Nicholas Piggin, 2023/05/15
Re: [PATCH v3 0/9] target/ppc: Assorted ppc target fixes, Daniel Henrique Barboza, 2023/05/27