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[PULL 49/60] ppc/pnv: Log all unimp warnings with similar message
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 49/60] ppc/pnv: Log all unimp warnings with similar message |
Date: |
Fri, 7 Jul 2023 08:30:57 -0300 |
From: Joel Stanley <joel@jms.id.au>
Add the function name so there's an indication as to where the message
is coming from. Change all prints to use the offset instead of the
address.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230706024528.40065-1-joel@jms.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/pnv_core.c | 34 ++++++++++++++++++----------------
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 8a72171ce0..a59f3f303d 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -85,8 +85,8 @@ static uint64_t pnv_core_power8_xscom_read(void *opaque,
hwaddr addr,
val = 0x24f000000000000ull;
break;
default:
- qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
- addr);
+ qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
+ offset);
}
return val;
@@ -95,8 +95,10 @@ static uint64_t pnv_core_power8_xscom_read(void *opaque,
hwaddr addr,
static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t
val,
unsigned int width)
{
- qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
- addr);
+ uint32_t offset = addr >> 3;
+
+ qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
+ offset);
}
static const MemoryRegionOps pnv_core_power8_xscom_ops = {
@@ -140,8 +142,8 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque,
hwaddr addr,
val = 0;
break;
default:
- qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
- addr);
+ qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
+ offset);
}
return val;
@@ -157,8 +159,8 @@ static void pnv_core_power9_xscom_write(void *opaque,
hwaddr addr, uint64_t val,
case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
break;
default:
- qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx
"\n",
- addr);
+ qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
+ offset);
}
}
@@ -189,8 +191,8 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque,
hwaddr addr,
val = 0;
break;
default:
- qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
- addr);
+ qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
+ offset);
}
return val;
@@ -203,8 +205,8 @@ static void pnv_core_power10_xscom_write(void *opaque,
hwaddr addr,
switch (offset) {
default:
- qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx
"\n",
- addr);
+ qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
+ offset);
}
}
@@ -419,7 +421,7 @@ static uint64_t pnv_quad_power9_xscom_read(void *opaque,
hwaddr addr,
val = 0;
break;
default:
- qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__,
+ qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
offset);
}
@@ -436,7 +438,7 @@ static void pnv_quad_power9_xscom_write(void *opaque,
hwaddr addr, uint64_t val,
case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
break;
default:
- qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
+ qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
offset);
}
}
@@ -463,7 +465,7 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque,
hwaddr addr,
switch (offset) {
default:
- qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__,
+ qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
offset);
}
@@ -477,7 +479,7 @@ static void pnv_quad_power10_xscom_write(void *opaque,
hwaddr addr,
switch (offset) {
default:
- qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
+ qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
offset);
}
}
--
2.41.0
- [PULL 41/60] ppc440: Add busnum property to PCIe controller model, (continued)
- [PULL 41/60] ppc440: Add busnum property to PCIe controller model, Daniel Henrique Barboza, 2023/07/07
- [PULL 39/60] ppc440: Rename local variable in dcr_read_pcie(), Daniel Henrique Barboza, 2023/07/07
- [PULL 43/60] ppc/sam460ex: Remove address_space_mem local variable, Daniel Henrique Barboza, 2023/07/07
- [PULL 44/60] ppc440_pcix: Don't use iomem for regs, Daniel Henrique Barboza, 2023/07/07
- [PULL 42/60] ppc440: Remove ppc460ex_pcie_init legacy init function, Daniel Henrique Barboza, 2023/07/07
- [PULL 45/60] ppc440_pcix: Stop using system io region for PCI bus, Daniel Henrique Barboza, 2023/07/07
- [PULL 46/60] ppc4xx_pci: Rename QOM type name define, Daniel Henrique Barboza, 2023/07/07
- [PULL 47/60] ppc4xx_pci: Add define for ppc4xx-host-bridge type name, Daniel Henrique Barboza, 2023/07/07
- [PULL 48/60] ppc440_pcix: Rename QOM type define abd move it to common header, Daniel Henrique Barboza, 2023/07/07
- [PULL 50/60] ppc/pnv: Set P10 core xscom region size to match hardware, Daniel Henrique Barboza, 2023/07/07
- [PULL 49/60] ppc/pnv: Log all unimp warnings with similar message,
Daniel Henrique Barboza <=
- [PULL 51/60] tests/qtest: Add xscom tests for powernv10 machine, Daniel Henrique Barboza, 2023/07/07
- [PULL 52/60] target/ppc: Machine check on invalid real address access on POWER9/10, Daniel Henrique Barboza, 2023/07/07
- [PULL 53/60] target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h', Daniel Henrique Barboza, 2023/07/07
- [PULL 54/60] target/ppc: Reorder #ifdef'ry in kvm_ppc.h, Daniel Henrique Barboza, 2023/07/07
- [PULL 55/60] target/ppc: Move CPU QOM definitions to cpu-qom.h, Daniel Henrique Barboza, 2023/07/07
- [PULL 56/60] target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h, Daniel Henrique Barboza, 2023/07/07
- [PULL 57/60] target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c, Daniel Henrique Barboza, 2023/07/07
- [PULL 58/60] target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h', Daniel Henrique Barboza, 2023/07/07
- [PULL 59/60] ppc/pnv: Add QME region for P10, Daniel Henrique Barboza, 2023/07/07
- [PULL 60/60] ppc: Enable 2nd DAWR support on p10, Daniel Henrique Barboza, 2023/07/07