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[PULL 51/60] tests/qtest: Add xscom tests for powernv10 machine
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 51/60] tests/qtest: Add xscom tests for powernv10 machine |
Date: |
Fri, 7 Jul 2023 08:30:59 -0300 |
From: Nicholas Piggin <npiggin@gmail.com>
Add basic chip and core xscom tests for powernv10 machine, equivalent
to tests for powernv8 and 9.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230706053923.115003-3-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
tests/qtest/pnv-xscom-test.c | 45 ++++++++++++++++++++++++++++--------
1 file changed, 36 insertions(+), 9 deletions(-)
diff --git a/tests/qtest/pnv-xscom-test.c b/tests/qtest/pnv-xscom-test.c
index 2c46d5cf6d..8a5ac11037 100644
--- a/tests/qtest/pnv-xscom-test.c
+++ b/tests/qtest/pnv-xscom-test.c
@@ -15,6 +15,7 @@ typedef enum PnvChipType {
PNV_CHIP_POWER8, /* AKA Venice */
PNV_CHIP_POWER8NVL, /* AKA Naples */
PNV_CHIP_POWER9, /* AKA Nimbus */
+ PNV_CHIP_POWER10,
} PnvChipType;
typedef struct PnvChip {
@@ -46,13 +47,22 @@ static const PnvChip pnv_chips[] = {
.cfam_id = 0x220d104900008000ull,
.first_core = 0x0,
},
+ {
+ .chip_type = PNV_CHIP_POWER10,
+ .cpu_model = "POWER10",
+ .xscom_base = 0x000603fc00000000ull,
+ .cfam_id = 0x120da04900008000ull,
+ .first_core = 0x0,
+ },
};
static uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba)
{
uint64_t addr = chip->xscom_base;
- if (chip->chip_type == PNV_CHIP_POWER9) {
+ if (chip->chip_type == PNV_CHIP_POWER10) {
+ addr |= ((uint64_t) pcba << 3);
+ } else if (chip->chip_type == PNV_CHIP_POWER9) {
addr |= ((uint64_t) pcba << 3);
} else {
addr |= (((uint64_t) pcba << 4) & ~0xffull) |
@@ -82,6 +92,8 @@ static void test_cfam_id(const void *data)
if (chip->chip_type == PNV_CHIP_POWER9) {
machine = "powernv9";
+ } else if (chip->chip_type == PNV_CHIP_POWER10) {
+ machine = "powernv10";
}
qts = qtest_initf("-M %s -accel tcg -cpu %s",
@@ -96,23 +108,36 @@ static void test_cfam_id(const void *data)
(PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
#define PNV_XSCOM_P9_EC_BASE(core) \
((uint64_t)(((core) & 0x1F) + 0x20) << 24)
+#define PNV_XSCOM_P10_EC_BASE(core) \
+ ((uint64_t)((((core) & ~0x3) + 0x20) << 24) + 0x20000 + \
+ (0x1000 << (3 - (core & 0x3))))
#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
static void test_xscom_core(QTestState *qts, const PnvChip *chip)
{
- uint32_t first_core_dts0 = PNV_XSCOM_EX_DTS_RESULT0;
- uint64_t dts0;
+ if (chip->chip_type == PNV_CHIP_POWER10) {
+ uint32_t first_core_thread_state =
+ PNV_XSCOM_P10_EC_BASE(chip->first_core) + 0x412;
+ uint64_t thread_state;
+
+ thread_state = pnv_xscom_read(qts, chip, first_core_thread_state);
- if (chip->chip_type != PNV_CHIP_POWER9) {
- first_core_dts0 |= PNV_XSCOM_EX_BASE(chip->first_core);
+ g_assert_cmphex(thread_state, ==, 0);
} else {
- first_core_dts0 |= PNV_XSCOM_P9_EC_BASE(chip->first_core);
- }
+ uint32_t first_core_dts0 = PNV_XSCOM_EX_DTS_RESULT0;
+ uint64_t dts0;
- dts0 = pnv_xscom_read(qts, chip, first_core_dts0);
+ if (chip->chip_type == PNV_CHIP_POWER9) {
+ first_core_dts0 |= PNV_XSCOM_P9_EC_BASE(chip->first_core);
+ } else { /* POWER8 */
+ first_core_dts0 |= PNV_XSCOM_EX_BASE(chip->first_core);
+ }
- g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull);
+ dts0 = pnv_xscom_read(qts, chip, first_core_dts0);
+
+ g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull);
+ }
}
static void test_core(const void *data)
@@ -123,6 +148,8 @@ static void test_core(const void *data)
if (chip->chip_type == PNV_CHIP_POWER9) {
machine = "powernv9";
+ } else if (chip->chip_type == PNV_CHIP_POWER10) {
+ machine = "powernv10";
}
qts = qtest_initf("-M %s -accel tcg -cpu %s",
--
2.41.0
- [PULL 39/60] ppc440: Rename local variable in dcr_read_pcie(), (continued)
- [PULL 39/60] ppc440: Rename local variable in dcr_read_pcie(), Daniel Henrique Barboza, 2023/07/07
- [PULL 43/60] ppc/sam460ex: Remove address_space_mem local variable, Daniel Henrique Barboza, 2023/07/07
- [PULL 44/60] ppc440_pcix: Don't use iomem for regs, Daniel Henrique Barboza, 2023/07/07
- [PULL 42/60] ppc440: Remove ppc460ex_pcie_init legacy init function, Daniel Henrique Barboza, 2023/07/07
- [PULL 45/60] ppc440_pcix: Stop using system io region for PCI bus, Daniel Henrique Barboza, 2023/07/07
- [PULL 46/60] ppc4xx_pci: Rename QOM type name define, Daniel Henrique Barboza, 2023/07/07
- [PULL 47/60] ppc4xx_pci: Add define for ppc4xx-host-bridge type name, Daniel Henrique Barboza, 2023/07/07
- [PULL 48/60] ppc440_pcix: Rename QOM type define abd move it to common header, Daniel Henrique Barboza, 2023/07/07
- [PULL 50/60] ppc/pnv: Set P10 core xscom region size to match hardware, Daniel Henrique Barboza, 2023/07/07
- [PULL 49/60] ppc/pnv: Log all unimp warnings with similar message, Daniel Henrique Barboza, 2023/07/07
- [PULL 51/60] tests/qtest: Add xscom tests for powernv10 machine,
Daniel Henrique Barboza <=
- [PULL 52/60] target/ppc: Machine check on invalid real address access on POWER9/10, Daniel Henrique Barboza, 2023/07/07
- [PULL 53/60] target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h', Daniel Henrique Barboza, 2023/07/07
- [PULL 54/60] target/ppc: Reorder #ifdef'ry in kvm_ppc.h, Daniel Henrique Barboza, 2023/07/07
- [PULL 55/60] target/ppc: Move CPU QOM definitions to cpu-qom.h, Daniel Henrique Barboza, 2023/07/07
- [PULL 56/60] target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h, Daniel Henrique Barboza, 2023/07/07
- [PULL 57/60] target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c, Daniel Henrique Barboza, 2023/07/07
- [PULL 58/60] target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h', Daniel Henrique Barboza, 2023/07/07
- [PULL 59/60] ppc/pnv: Add QME region for P10, Daniel Henrique Barboza, 2023/07/07
- [PULL 60/60] ppc: Enable 2nd DAWR support on p10, Daniel Henrique Barboza, 2023/07/07
- Re: [PULL 00/60] ppc queue, Daniel Henrique Barboza, 2023/07/07