Re: [PATCH 08/12] target/loongarch: Use generic hrev64_i64() in REVB.4H opcode

[Philippe Mathieu-Daudé]

On 22/8/23 15:28, Philippe Mathieu-Daudé wrote:
> On 22/8/23 14:51, Philippe Mathieu-Daudé wrote:
> > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> > ---
> >   target/loongarch/insn_trans/trans_bit.c.inc | 15 +--------------
> >   1 file changed, 1 insertion(+), 14 deletions(-)
> >
> > diff --git a/target/loongarch/insn_trans/trans_bit.c.inc 
> > b/target/loongarch/insn_trans/trans_bit.c.inc
> > index 95b4ee5bc8..c04806dc21 100644
> > --- a/target/loongarch/insn_trans/trans_bit.c.inc
> > +++ b/target/loongarch/insn_trans/trans_bit.c.inc
> > @@ -124,19 +124,6 @@ static void gen_revb_2h(TCGv dest, TCGv src1)
> >       tcg_gen_or_tl(dest, t0, t1);
> >   }
> > -static void gen_revb_4h(TCGv dest, TCGv src1)
> > -{
> > -    TCGv mask = tcg_constant_tl(0x00FF00FF00FF00FFULL);
> > -    TCGv t0 = tcg_temp_new();
> > -    TCGv t1 = tcg_temp_new();
> > -
> > -    tcg_gen_shri_tl(t0, src1, 8);
> > -    tcg_gen_and_tl(t0, t0, mask);
> > -    tcg_gen_and_tl(t1, src1, mask);
> > -    tcg_gen_shli_tl(t1, t1, 8);
> > -    tcg_gen_or_tl(dest, t0, t1);
> > -}
> > -
> >   static void gen_revh_2w(TCGv dest, TCGv src1)
> >   {
> >       TCGv_i64 t0 = tcg_temp_new_i64();
> > @@ -175,7 +162,7 @@ TRANS(clz_d, gen_rr, EXT_NONE, EXT_NONE, gen_clz_d)
> >   TRANS(cto_d, gen_rr, EXT_NONE, EXT_NONE, gen_cto_d)
> >   TRANS(ctz_d, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_d)
> >   TRANS(revb_2h, gen_rr, EXT_NONE, EXT_SIGN, gen_revb_2h)
> > -TRANS(revb_4h, gen_rr, EXT_NONE, EXT_NONE, gen_revb_4h)
> > +TRANS(revb_4h, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_hrev64_i64)
>
> We should use tcg_gen_hrev64_tl() instead.

Although due to the 0x00FF00FF00FF00FFULL constant it
seems gen_revb_4h() really expects i64 registers...
(see gen_revh_2w which uses TCGv_i64).

I suppose gen_revb_4h() ended that way as a copy/paste of
gen_revb_2h().