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[PATCH 03/13] ppc/spapr|pnv: Remove SAO from pa-features
From: |
Nicholas Piggin |
Subject: |
[PATCH 03/13] ppc/spapr|pnv: Remove SAO from pa-features |
Date: |
Tue, 12 Mar 2024 04:51:45 +1000 |
SAO is a page table attribute that strengthens the memory ordering of
accesses. QEMU with MTTCG does not implement this, so clear it in
ibm,pa-features. This is an obscure feature that has been removed from
POWER10 ISA v3.1, there isn't much concern with removing it.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 2 +-
hw/ppc/spapr.c | 14 ++++++++++----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0b47b92baa..aa9786e970 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -150,7 +150,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void
*fdt)
uint32_t page_sizes_prop[64];
size_t page_sizes_prop_size;
const uint8_t pa_features[] = { 24, 0,
- 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
+ 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0,
0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 55263f0815..5099f12cc6 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -234,16 +234,16 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
void *fdt, int offset)
{
uint8_t pa_features_206[] = { 6, 0,
- 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
+ 0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 };
uint8_t pa_features_207[] = { 24, 0,
- 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
+ 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0,
0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
uint8_t pa_features_300[] = { 66, 0,
/* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
- /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
- 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
+ /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
+ 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
/* 6: DS207 */
0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
/* 16: Vector */
@@ -284,6 +284,12 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
return;
}
+ /*
+ * SSO (SAO) ordering is supported on KVM and thread=single hosts,
+ * but not MTTCG, so disable it. To advertise it, a cap would have
+ * to be added, or support implemented for MTTCG.
+ */
+
if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
/*
* Note: we keep CI large pages off by default because a 64K capable
--
2.42.0
- Re: [PATCH 01/13] ppc: Drop support for POWER9 and POWER10 DD1 chips, (continued)
[PATCH 02/13] target/ppc: POWER10 does not have transactional memory, Nicholas Piggin, 2024/03/11
[PATCH 04/13] ppc/spapr: Remove copy-paste from pa-features, Nicholas Piggin, 2024/03/11
[PATCH 05/13] ppc/spapr: Adjust ibm,pa-features for POWER9, Nicholas Piggin, 2024/03/11
[PATCH 03/13] ppc/spapr|pnv: Remove SAO from pa-features,
Nicholas Piggin <=
[PATCH 06/13] ppc/spapr: Add pa-features for POWER10 machines, Nicholas Piggin, 2024/03/11
Re: [PATCH 06/13] ppc/spapr: Add pa-features for POWER10 machines, Nicholas Piggin, 2024/03/12
Re: [PATCH 06/13] ppc/spapr: Add pa-features for POWER10 machines, Harsh Prateek Bora, 2024/03/12